NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 78

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6 6
G E N m o d u l e r e g i s t e r s
Table 24: System Control register bit definition
D12
D11
D10
D09:08
D07
D06
Bits
R/W
R/W
R/W
N/A
R/W
R/W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
DMATST
TEALAST
MISALIGN
Reserved
CPUDIS
DMARST
Mnemonic
0
0
0
N/A
-ADDR26
0
Reset
DMA module test mode
Resets the DMA controller subsystem. Also allows the
ARM processor direct access to the internal context RAM
found in the DMA controller.
Bus interface TEA/LAST configuration
This bit can be read or written with a setting of 1 or 0, but
has no effect on chip functionality.
Bus error on misaligned cycles
0
1
When this bit is set to 1, misaligned address transfers
cause a data abort to be issued to the offending bus master.
A misaligned address transfer is defined as a half word
access to an odd byte address boundary, or a full word
access to either a half word or byte address boundary.
This bit is useful during software debugging to detect
misaligned cycles.
N/A
CPU disable
0
1
Provides a mechanism to read back the bootstrap value of
ADDR26 (see "NS7520 bootstrap initialization" on page
59). If this bit is set to 1, the CPU is disabled.
DMA module reset
0
1
Provides a mechanism to issue a soft reset to the DMA
module without affecting any other modules.
Description
controller subsystem is held in reset and the ARM
processor can access all internal DMA context RAM.
This is useful for diagnostic purposes.
controller subsystem operates normally. Only the bits
in the DMA Control register space can be accessed
by the ARM processor.
Disable misaligned data transfer bus abort generation
Generate a bus abort during a misaligned transfer
CPU operational
CPU reset
DMA module operational
DMA module (held in) reset
When set to 1 (allow unrestricted access), the DMA
When set to 0 (test mode disabled), the DMA