NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 231

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6
SPI slave transmitter
The SPI slave transmitter operates as follows:
SPI slave receiver
The SPI slave receiver operates as follows:
–
–
–
Configure Serial Channel Control Register A, as shown:
–
–
Has the first bit ready for transmission before the SPI enable signal is
activated by the SPI master.
Changes the TXD output to the next data bit for transmission on the rising
edge of the SPI clock, while the SPI enable signal is active low.
Goes through a sampling of the SPI clock input. The output changes 3 to 4
internal system clock ticks from the rising edge of the SPI clock input. The
SPI master receiver does not sample the changing data until the next rising
edge of SPI clock.
Continues to change TXD data bits on the rising edge of SPI clock until the
SPI enable signal is driven inactive high. While the SPI enable signal is
inactive high, the TXD output remains constant.
Samples the RXD input on the rising edge of the SPI clock signal while the
SPI enable signal is driven active low. The SPI slave receiver actually goes
through a sampling of the SPI input, which means the input is sampled 3 to 4
internal system clock ticks from the rising edge of the SPI clock input.
When the SPI slave receiver collects four bytes, these four bytes are written
to the RX FIFO. Receive data is read by the CPU or DMA controller from the
other side of the FIFO. If the SPI master transmitter always sends data in
multiples of four bytes, the SPI slave receiver operates smoothly without
any restrictions.
When the master SPI transmitter sends an odd number of bytes, the SPI
slave receiver waits for the fourth byte before insertion into the FIFO. This
can result in stale data sitting in the SPI slave receiver. To commit these
RCGT: 1 to enable the character GAP timer
MODE: 11 for slave mode
BITORDR: user-defined
CE: 1 for enable
WLS: 11 for 8-bit operation
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