NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 92

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8 0
I n t e r r u p t s
Interrupts
READBACK
When reading the CDATA field, the data read depends on how the pin is configured:
PORTC4
When PORTC is configured with
Serial Channel B determines the function
SER2_OUT1
RESET_ output.
PORTC0
When PORTC0 is configured with
Serial Channel B determines the function
PORTC[3:0]
These pins can be programmed individually to generate level-sensitive interrupts.
Level-sensitive interrupts generate an interrupt when the input signal matches the
state of the corresponding DIR bit. The interrupt condition persists until the input
signal changes state or the configuration is changed.
There are two wires that go to the CPU core and interrupt the processor:
FIRQ has higher priority than IRQ, providing a simple two-tier priority scheme to the
interrupt system. Most sources of interrupts on the NS7520 come from the IRQ line.
FIRQ interrupt sources are the three built-in timers and the watchdog timer,
controlled by the Timer 1/2 and Status registers and the System Control register,
respectively.
Configured as GPIO output. Reads data from the register whose data drives
the pin. This can, for example, mask a short circuit on the output pin.
All other configurations. Reads the state of the pin.
IRQ. Normal interrupt.
FIRQ. Fast interrupt.
. Following external reset,
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
CSF[4]=1:CMODE[4]=1:CDIR[4]=1
CSF[0]=1:CMODE[0]=1:CDIR[0]=1
CSF[4]=0:CMODE[4]=1:CDIR[4]=1
SER2
SER2_SPI_M_ENABLE_OUT
_
SPI_M_CLK_OUT, SER2_TXC_OUT,
, the configuration of
, the configuration of
; that is, set to drive
or
SER2
_
OUT2
or
.