NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 258

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2 4 6
S e r i a l C h a n n e l r e g i s t e r s
Table 90: Serial Channel Bit-Rate register bit definition
D17:16
D15
D14
Bits
R/W
N/A
R/W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
RDCR
Reserved
TICS
Mnemonic
0
N/A
0
Reset
Receive divide clock rate
00
01
10
11
Determine the oversampling multiplier for the
transmitter and receiver clocks.
The TMODE bit in the Serial Channel Bit-Rate
register is maintained for NET+ARM family
backward compatibility. When setting TDCR or
RDCR to a non-zero value, the TMODE must be set
to 1. When the TMODE, TDCR, and RDCR fields are
set to 0, the port defaults to 16x mode of operation.
N/A
Transmit internal clock source
0
1
When the TXSRC field is set to 0, the transmitter
operates using an internal clock. There are two
sources for internal clocks: the bit-rate generator
(BRG) and the receiver digital phase lock loop
(DPLL). The BRG uses a divider mechanism for
clock generation. The DPLL extracts the clock from
the incoming receive data stream.
Description
UART, select the value 1x.
select 8x, 16x, or 32x (16x is recommended).
In most applications, the TDCR and RDCR
configurations should match.
selected TDCR/RDCR value is a function of the
transmitter encoding. NRZ and NRZI modes can
use the 1x configuration; all other encoding must
use 8x, 16x, or 32x configuration mode. 8x
configuration provides the highest data rate; 32x
mode provides the highest resolution.
BRG; the transmitter uses BRG output for its
clock
DPLL; the transmitter uses the extracted clock
provided by the DPLL.
If DPLL is not used and you are not using
If DPLL is not used but you are using UART,
When DPLL is used in the application, the
1x clock mode (only NRZ or NRZI allowed)
8x clock mode
16x clock mode
32x clock mode