NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 253

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Serial Channel 1, 2 Bit-Rate registers
Table 89: Serial Channel Status Register A bit definition
Address: FFD0 000C / 4C
The serial channel bit rate registers configure the bit-rate for each serial channel.
The serial channel can be configured to operate using an internal or external timing
reference. When configured for internal timing, the timing reference is provided by
the bit-rate generator. When configured for external timing, the timing reference is
provided by the PORTC signals RXCLK and TXCLK.
The serial channel can be configured to operate in either 1X (synchronous) mode or
16X (asynchronous) mode. When using the internal bit-rate generator, the frequency
must be configured properly to match the mode being used.
D01
TBC continued
D00
Bits
R/C
R
Access
TBC
TEMPTY
Mnemonic
0
0
Reset
Transmit buffer closed interrupt pending
Indicates a transmit buffer closed condition. Once set,
the TBC bit remains set until acknowledged. TBC is
acknowledged by writing a 1 to this same bit position
in this register. The TBC bit is acknowledged
automatically by hardware when the transmitter is
configured to operate in DMA mode. The TBC status
condition can be programmed to generate an interrupt
by setting the related IE bit in Serial Channel Control
Register A.
The TBC field is set when the last character in the
transmit FIFO has been shifted out of the shift register
and the FIFO currently is empty. While the TBC field
is active, the TRDY bit is not active. To activate
TRDY (to write to the data FIFO), TBC must be
acknowledged. When operating in DMA mode, the
interlock between TBC and TRDY is handled
automatically in hardware.
Transmit FIFO empty
Indicates that the transmit data FIFO is currently
empty. TEMPTY simply reports the status of the
FIFO; it does not indicate that the character currently
in the transmit shift register has been transmitted. The
TBC bit must be used for the all sent condition.
Description
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