NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 121

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DRAM refresh
FP/EDO DRAM controller
Setting the DMUXS bit indicates that the internal address multiplexer must be
disabled when the specific chip select is activated. The NS7520 drives the address bus
using standard addressing without any multiplexing, but only for the specific chip
select, the internal address multiplexer is disabled, and the multiplexer indicator is
driven out the PORTA2 pin.
The PORTA2 signal is driven active high during the CAS addressing portion for FP and
EDO DRAM, as well as during the SDRAM write command, read command, and load
mode command. The NS7520 drives the SDRAM load mode command on its lower
address pins. At all other times, the PORTA2 signal is driven active low.
The NS7520 MEM module executes a refresh cycle that supports Fast Page (FP), EDO
and SDRAM devices. The FP and EDO devices are refreshed using the CAS-before-RAS
technique; SDRAM devices re refreshed using the REFRESH command.
"fp_refresh_cycles" on page 288 provides a timing diagram of DRAM refresh cycles
based in the RCYC setting. This diagram illustrates the CAS-before-RAS refresh cycles
for FP and EDO DRAM. The RCYC field controls the timing of CAS and RAS in the
refresh cycle.
The memory controller module contains an integrated FP/EDO DRAM controller. Each
chip select can be configured to operate using DRAM. The DRAM controller supports
these features:
FP (Fast Page) mode, EDO DRAMs, and SDRAM (see "SDRAM," beginning on
page 111).
CAS before RAS refresh operation
Programmable refresh timer
Background refresh cycles (refresh while another non-DRAM chip select
access is in progress)
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