NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 249

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 89: Serial Channel Status Register A bit definition
D15
D14
D13
D12
Bits
R/C
R/C
R/C
R/C
Access
RBRK
RFE
RPE
ROVER
Mnemonic
0
0
0
0
Reset
Receive break interrupt pending
Indicates that a UART receive break condition has
been found. Once set, the RBRK bit remains set until
acknowledged. RBRK is acknowledged by writing a
1 to this same bit position in this register.
The RBRK status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
Receive framing error interrupt pending
Indicates that a receive framing error condition has
been found. Once set, the RFE bit remains set until
acknowledged. RFE is acknowledged by writing a 1
to this same bit position in this register.
The RFE status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
Receive parity error interrupt pending
Indicates that a receive parity error condition has been
found. Once set, the RPE field remains set until
acknowledged. RPE is acknowledged by writing to
this same bit position in this register.
The RPE status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
Receive overrun interrupt pending
Indicates that a receive overrun error condition has
been found. An overrun condition indicates that the
FIFO was full while data needed to be written by the
receiver. When the FIFO is full, any new receive data
will be discarded; the contents of the FIFO before the
overrun condition remains the same.
Once set, the ROVER field remains set until
acknowledged. ROVER is acknowledged by writing a
1 to this same bit position in this register.
The ROVER status condition can be programmed to
generate an interrupt by setting the related IE bit in the
Serial Channel Control Register A.
Description
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S e r i a l C o n t r o l l e r M o d u l e
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