NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 238

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2 2 6
S e r i a l C h a n n e l r e g i s t e r s
Table 85: Serial Channel Control Register A
D16
D15:09
D08
D07:05
Bits
R/W
R/W
R/W
R/W
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
RTS
IE
ERXDMA
IE
Mnemonic
0
0
0
0
Reset
Request-to-send active
Controls the state of the external request-to- send
signal.
Receiver interrupt condition
The interrupt enable bits are used to enable an
interrupt when the respective status bit is set in Serial
Channel Status A.
Table 86, “Receiver interrupt enable bits,” on
page 227, lists individual bit numbers and
descriptions.
Enable receive DMA requests
Enables the receiver to interact with a DMA channel.
When configured to operate in DMA mode, the DMA
controller empties the receive data FIFO and delivers
the data to memory. The receive status information
from Serial Status registers B and C automatically
moves to the receive DMA buffer descriptor.
Clear this bit to pause the receiver.
Receiver interrupt condition
The interrupt enable bits are used to enable an
interrupt when the respective status bit is set in Serial
Channel Status A.
Table 86, “Receiver interrupt enable bits,” on
page 227, lists individual bit numbers and
descriptions.
Description
active.
inactive.
Setting RTS to 1 causes the RTS output to go
Setting RTS to 0 causes the RTS output to go
Setting the IE field to 1 enables the interrupt.
Setting the IE field to 0 disables the interrupt.
Setting the IE field to 1 enables the interrupt.
Setting the IE field to 0 disables the interrupt.