NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 184

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1 7 2
E F E c o n f i g u r a t i o n
Table 58: Ethernet Transmit Status register bit definition
D06
D05
D04
D03:00
Bits
R
R
N/A
R
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
TXDEF
TXCRC
Not used
TXCOLC
Mnemonic
0
0
0
0
Reset
Transmit packet deferred
Set to 1 to indicate that the last successfully transmitted
Ethernet packet encountered a deferral. Transmission was
delayed because the Ethernet medium was busy when
trying to send the first transmission.
When this bit is set (instead of TXOK or any of the TX
abort bits), the transmitter tries to resend the packet. This
process continues until the packet is transmitted
successfully or an abort condition is detected. A change in
transmit error bits can be determined only by polling.
Transmit CRC error
Set to 1 to indicate that the last successfully transmitted
Ethernet packet had an embedded CRC error. This
condition occurs only when the CRCEN bit in the MAC
Configuration register is set to 0.
When CRCEN is set to 0, the MAC does not insert a CRC;
the MAC expects a precompiled CRC to be contained in
the last four bytes of the Ethernet packet. If the MAC finds
that the precompiled CRC is incorrect, the MAC sets the
TXCRC bit in this (Ethernet Transmit Status) register.
When this bit is set (instead of TXOK or any of the TX
abort bits), the transmitter tries to resend the packet. This
process continues until the packet is transmitted
successfully or an abort condition is detected. A change in
transmit error bits can be determined only by polling.
Always 0.
Transmit collision count
Indicates how many collisions the MAC encountered while
it was trying to transmit the package. TXCOLC indicates
only that collision events have occurred; if the packet
transmission was aborted, the TXAEC bit will be set.
The MAC tries to retransmit the packet up to the maximum
number of collision retries defined by the RETRY field in
the Collision Window/Collision Retry register.
This bit is valid (1) when the TXAL or TXAEC bits are set;
otherwise, the bit is set to 0.
Description