NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 60

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4 8
S i g n a l d e s c r i p t i o n
Signal description
JTAG support
ARM debug
The system control signals determine the basic operation of the chip:
The NS7520 provides full support for 1149.1 JTAG boundary scan testing. All NS7520
pins can be controlled using the JTAG interface port. The JTAG interface provides
access to the ARM7TDMI debug module when the appropriate combination of
BISTEN_,
configuration," beginning on page 50).
The ARM7TDMI core uses a JTAG TAP controller that shares pins with the TAP
controller used for 1149.1 JTAG boundary scan testing. To enable the ARM7TDMI TAP
{XTALA1, XTALA2}
{PLLVDD, PLLVSS}
RESET_
{TDI, TDO, TNS, TRST_,
TCK}
{PLLTEST_, BISTEN_,
SCANEN_}
Signal mnemonic
and
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
SCANEN_
are selected (see "External oscillator mode hardware
Clock source
PLL power
Chip reset
JTAG interface
Chip mode
Signal name
Operate in one of two ways:
Provide an isolated power supply for the PLL.
Active low signal asserted to initiate a hardware
reset of the chip.
Provide a JTAG interface for the chip. This
interface is used for both boundary scan and ICE
control of the internal processor.
Encoded to determine the chip mode.
Description
parallel mode quartz crystal or crystal
oscillator and the appropriate components
per the component manufacturer.
XTALA2 is left open.
The signals are affixed with a 10-20 MHz
XTALA1 is driven with a clock signal and
PLLTST_,