NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 226

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2 1 4
S P I m o d e
active high. This long word can have 1, 2, 3, or 4 bytes of valid data within the word.
The number of valid bytes is determined by the bit encoding in the RXFDB field in
Serial Channel Status Register A. The RXFDB field must be read before the FIFO Data
register is read.
The RBC (receive buffer closed) bit in Serial Channel Status register A indicates that a
receive data buffer has been closed and receiver status can be read from that
register. Before additional data can be read from the FIFO, the RBC bit must be
acknowledged by writing a 1 to the same bit position in the Serial Channel Status
Register A.
This is the recommended process flow for the serial port receiver interrupt service
routine:
1
2
3
Using DMA
When using the DMA controller, the processor must interface with the DMA channel
registers and the DMA buffer descriptor block attached to DMA channels 7 and 9. To
facilitate the use of receive DMA, the ERXDMA bit in Serial Channel Control Register A
must be set active high and the serial receiver interrupts should be disabled.
SPI master mode
SPI master mode controls the flow of data between memory in the master SPI
interface and an external SPI slave peripheral. The SPI master determines the
Read Serial Channel Status Register A.
If RBC is true:
a
b
c
If RRDY is true:
a
b
To facilitate an interrupt when either the RRDY or RBC status bits are
active, the processor must set one or both of the corresponding interrupt
enables — ERXDRDY, ERXBC — in Serial Channel Control Register A. The
appropriate interrupt enable bit — SER 1 RX, SER 2 RX — in the GEN module
Interrupt Enable register must also be set.
Record receiver buffer closed status (if desired).
Write a 1 to the RBC bit position in Serial Channel Status Register A.
Read Serial Channel Status Register A again.
Read the data FIFO.
Use the RXFDB field to pick valid bytes.
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7