NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 47

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

After emulating the failed instruction, the trap handler should execute the following
instruction irrespective of the state (Thumb or ARM):
This instruction restores the PC and CPSR, and returns to the instruction following the
undefined instruction.
SWI exception
An SWI is used for entering supervisor mode, usually to request a particular supervisor
function. An SWI handler should return by executing this instruction irrespective of
the state (ARM or Thumb):
This instruction restores the PC and CPSR, and returns to the instruction following the
SWI.
Abort exception
An abort indicates that the current memory access cannot be completed, and is
signaled by the external ABORT input. The ARM7TDMI checks for the abort exception
during memory access cycles.
There are two types of abort exception:
Prefetch abort. Occurs during an instruction prefetch. If a prefetch abort
occurs, the prefetch instruction is marked as invalid but the exception is
not taken until the instruction reaches the head of the pipeline. If the
instruction is not executed (for example, if a branch occurs while the
instruction is in the pipeline), the abort does not take place.
Data abort. Occurs during a data operand access. If a data abort occurs, the
action taken depends on the instruction type:
–
–
–
Single data transfer instructions (LDR, STR) write back modified base
registers; the abort handler must be aware of this.
A swap instruction (SWP) is aborted as though it had not been executed.
Block data transfer instructions (LDM, STM) complete. If write-back is set,
the base is updated. If the instruction would have overwritten the base with
data (that is, the base is in the transfer list), the overwriting is prevented.
All register overwriting is prevented after an abort is indicated, which
means that
aborted LDM instruction.
R15
(always the last register to be transferred) is preserved in an
MOVS PC, R14_SVC
.
w w w . d i g i e m b e d d e d . c o m
MOVS PC, R14_und.
W o r k i n g w i t h t h e C P U
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