NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 252

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

2 4 0
S e r i a l C h a n n e l r e g i s t e r s
Table 89: Serial Channel Status Register A bit definition
D05
D04
D03
D02
Bits
R/C
R/C
R
R
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
DSRI
CTSI
TRDY
THALF
Mnemonic
0
0
0
0
Reset
Change in DSR interrupt pending
Indicates a state change in the EIA data set ready
signal. Once set, the DSRI bit remains set until
acknowledged. DSRI is acknowledged by writing a 1
to this same bit position in this register.
The DSRI state condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
Change in CTS interrupt pending
Indicates a state change in the EIA clear to send
signal. Once set, the CTSI bit remains set until
acknowledged. CTSI is acknowledged by writing a 1
to this same bit position in this register.
The CTSI state condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
Transmit register empty interrupt pending
Indicates data can be written to the FIFO Data
register. TRDY typically is used only in interrupt-
driven applications; it is not used for DMA operation.
The TRDY status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel Control Register A.
TRDY is never active while the TBC bit is active.
TBC must be acknowledged to activate the TRDY bit.
When the transmitter is configured to operate in DMA
mode, the interlock between TBC and TRDY is
handled automatically in hardware.
Transmit FIFO half-empty interrupt pending
Indicates that the transmit data FIFO contains room
for at least 16 bytes. The THALF field typically is
used only in interrupt-driven applications; it is not
used for DMA operation.
The THALF status condition can be programmed to
generate an interrupt by setting the related IE bit in
Serial Channel COntrol Register A.
Description