NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 331

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

E
EDO DRAM
EDO DRAM controller
EFE receive processing
EFE transmit processing
electrical characteristics
electrical specifications, AC
ENDEC
ENDEC mode and NS7520 pins
entering an exception
Ethernet FIFO Data register
Ethernet front-end.
Ethernet General Control register
Ethernet General Status register
Ethernet interface MAC
Ethernet MAC
Ethernet module
I -
burst cycles
interface
Level 1 mode
SEEQ mode
reading from
writing to
ENDEC mode bits
media control bits
pinout
signal descriptions
Back-to-Back Inter-Packet-Gap
calculating hash table entries
Collision Window/Collision Retry
DMA channel assignments for
EFE configuration
EFE module
features
high-level structure
18
register
register
Ethernet
86
3
167
3
161
150 - 153
111
150
167
149 - 205
161
182
184
See
156
158
109 - 111
156
37
158
19
151
EFE.
151
257 - 299
150
167
261
162
164
202
158
Ethernet General Control register
Ethernet General Status register
external CAM filtering
FIFO Data register
MAC Configuration register 1
MAC Configuration register 2
MAC module
Maximum Frame register
MII Management Address register
MII Management Command
MII Management Configuration
MII Management Indicators
MII Management Read Data
MII Management Write Data
multicast hash table entries
Non-Back-to-Back Inter-Packet-Gap
PHY Support register
Receive Status register
register hash table
SMII Status register
Station Address Filter register
Station Address registers
Test register
Transmit Status register
receive buffer descriptor
receive FIFO
receive processing
transmit FIFO
transmit processing
and MII
features
hierarchy
register
register
register
register
register
register
selection
154
154
154 - 155
187
154
191
189
195
194
193
183
151
151
167
200 - 205
196
152
186
153
151
173
151
168
185
196
I n d e x - 3
200
176
178
199
164
192
158