NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 336

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I n d e x -
8
SDRAM timing
Serial Channel 1,2 Bit-Rate registers
Serial Channel 1,2 Control Register A
Serial Channel 1,2 Control Register B
Serial Channel 1,2 FIFO registers
Serial Channel 1,2 Receive Buffer Gap
Serial Channel 1,2 Receive Character Gap
Serial Channel 1,2 Receive Match MASK
Serial Channel 1,2 Receive Match
Serial Channel 1,2 Status Register A
serial internal/external timing
serial interrupts
serial module
receiver interrupts
transmitter interrupts
and bit-rate generator
configuration
features
GPIO configurations
protocols
receiver interrupt enable bits
Serial Channel 1,2 Bit-Rate
Serial Channel 1,2 Control Register
Serial Channel 1,2 Control Register
Serial Channel 1,2 FIFO registers
Serial Channel 1,2 Receive Buffer Gap
Serial Channel 1,2 Receive Character
Serial Channel 1,2 Receive Match MASK
Serial Channel 1,2 Receive Match
Timer
Timer
register
register
registers
A
B
Timer
Gap Timer
register
208
229
223
210
250
252
207 - 255
277 - 282
254
254
40
221
250
254
241
252
227
220
228
209
297 - 298
250
227
233
241
250
223
229
serial port performance
serial ports
single data transfer instructions
SMII Status register
software action
software reset circuit source
Software Service register
SPI
SRAM controller
Serial Channel 1,2 Status Register
serial port performance
SPI mode
structure
transmitter interrupt enable bits
UART mode
controller features
FIFO management
master configuration
master mode
slave configuration
slave mode
burst cycles
single cycle read/write
211 - 220
FIFO management
master mode
receive FIFO interface
slave mode
transmit FIFO interface
configuration
receiver
signals
transmitter
configuration
receiver
signals
transmitter
register
A
3
233
211 - 220
209
215
218
217 - 220
210 - 211
37
104
216
219
102 - 105
214 - 217
217 - 220
254
216
219
196
214 - 217
215
218
212
211
211
221
211
69
212
102
221
59
213
212
35
228