NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 44

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Summary of ARM exceptions
Exception priorities
3 2
W o r k i n g w i t h A R M e x c e p t i o n s
The ARM processor can be interrupted by any of seven basic exceptions:
Several exceptions can occur at the same time. If this happens, a fixed-priority
system determines the order in which they are handled:
Reset exception. After a reset condition, the ARM7TDMI saves the current
values of the PC (program counter) and CPSR (Current Processor Status
register).
Undefined exception. The ARM7TDMI takes the undefined instruction trap
when it finds an instruction it cannot handle.
SWI instruction. The ARM7TDMI uses the software interrupt instruction
(SWI) to enter supervisor mode, usually to request a specific supervisor
instruction.
Abort exception. An abort exception indicates that the current memory
access cannot be completed. There are two types of abort exception:
–
–
IRQ. An interrupt request (IRQ) exception is a normal interrupt serviced by
the ARM7TDMI controller.
FIRQ. A fast interrupt request (FIRQ) exception supports a data transfer or
channel process. An FIRQ interrupt is generated only by the GEN module
timers and watchdog timer.
Highest priority
1
2
3
4
5
6
Lowest priority
Prefetch. Occurs during an instruction prefetch.
Data. Occurs during a data operand access.
Reset
Data abort
FIRQ
IRQ
Prefetch abort
Undefined instruction, SWI
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