NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 29

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 4: Chip select controller pinout
Signal descriptions
Table 5: Chip select controller signal description
CAS1_
CAS0_
WE_
OE_
CS0_
CS1_
CS2_
CS3_
CS4_
CAS0_
CAS1_
CAS2_
CAS3_
WE_
Symbol
Mnemonic
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Column address strobe
signals
Write enable
Signal
B3
A2
C6
B6
Pin
O
O
O
O
I/O
Unique chip select outputs supported by the NS7520. Each
chip select can be configured to decode a portion of the
available address space and can address a maximum of 256
Mbytes of address space. The chip selects are configured
using registers in the memory module.
A chip select signal is driven low to indicate the end of the
current memory cycle. For FP/EDO DRAM, these signals
provide the RAS signal.
Activated when an address is decoded by a chip select
module configured for DRAM mode. The CAS_ signals
are active low and provide the column address strobe
function for DRAM devices.
The CAS_ signals also identify which 8-bit bytes of the 32-
bit data bus are active during any given system bus memory
cycle.
For SDRAM, CAS[3:1]_ provides the SDRAM command
field. CAS0_ provides the
auto-precharge signal.
For non-DRAM settings, these signals are 1.
Active low signal that indicates that a memory write cycle
is in progress. This signal is activated only during write
cycles to peripherals controlled by one of the chip selects in
the memory module.
Description
4
4
4
4
OD
w w w . d i g i e m b e d d e d . c o m
FP/EDO DRAM column strobe
D15:D08/SDRAM WE_
FP/EDO DRAM column strobe
D07:D00/SDRAM A10(AP)
Write enable for NCC Ctrl’d cycles
Output enable for NCC Ctrl’d cycles
Description
P i n o u t a n d P a c k a g i n g
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