NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 134

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SDRAM write cycles
1 2 2
S D R A M
Figure 13 and Figure 14 provide timing diagrams for SDRAM normal and burst writes,
respectively, with WAIT and BCYC configured with a value of 0.
Figure 13: SDRAM normal write
TEA_(LAST_) {output}
TEA_(LAST_) {input}
wait states are inserted after the read command, depending on the value of
the BCYC configuration. The BCYC configuration identifies the CAS latency
specification for the SDRAM.
The burst stop command is issued at the end of the current burst read
operation. The SDRAM continues to burst read data for an additional
number of BCLK cycles after the burst stop command is issued. The number
of cycles is calculated as
than one, additional wait states are inserted between T2 and the next
system bus cycle to account for the delay. These additional bus cycles are
identified as TX states.
CAS3_(RAS_)
CAS2_(CAS_)
CAS1_(WE_)
TA_ {output}
TA_ {input}
CS[7:0]_
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
BE[3:0]
D[31:0]
A[13:0]
AMUX
BCLK
RW_
TS_
CAS latency - 1
precharge
. When the CAS latency value is greater
One Valid Per Cy cle
activ ate
write
bstop