NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 67

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 21: PLL Settings register bit definition
The next table shows the 32 frequencies that can be produced with an 18.432MHz
crystal. A 0 on an address indicates that a 2.7K pulldown resistor must be connected
to that address line. The table shows the IS, FS, and ND fields, and the resulting value
in the PLL Settings register.
D08:07
D06:05
D04:00
4.6
9.2
13.8
18.4
Bits
MHz
01
01
01
01
A[8:7]
Read
only
Read
only
Read
only
Access
00
00
00
01
IS
IS
FS
ND
Mnemonic
11
11
11
11
A[6:5]
‘b10
‘b00
‘b01011
Reset
00
00
00
00
FS
10100
10101
10110
10111
A[4:0]
Charge pump current
Sets the PLL’s charge pump current.
The IS field defaults to binary ‘b10 when address lines
[8:7] are not pulled down on powerup. The IS value is
based on the value in the ND field.
(ND+1)
1–3
4–7
8–15
16–32
Output divider
Sets the PLL’s output divider.
The FS field defaults to ‘b00 when address lines [6:5] are
not pulled down on powerup. This is the correct setting
for all frequencies and should never be adjusted.
PLL multiplier
Sets the PLL’s multiplier, which determines BCLK
frequency.
BCLK frequency is based on tis formula:
The ND field defaults to ‘b01011 to produce 55MHz
(with a 18.432MHz crystal) when address lines A[4:0]
are not pulled down on powerup.
Description
w w w . d i g i e m b e d d e d . c o m
BCLK = (crystal/4) (ND+1)
00001
00010
00011
00100
ND+1
0x00000000
0x00000001
0x00000002
0x00000003
PLL Settings reg
IS
‘b00
‘b01
‘b10
‘b11
S Y S M o d u l e
Notes
5 5