NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 155

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 51: DMA Status/Interrupt Enable register bit definition
D29
D28
D27
D26:25
D24
D23
D22
D21
Bits
R/C
R/C
R/C
N/A
R/W
R/W
R/W
R/W
Access
NRIP
CAIP
PCIP
Reserved
PCIE
NCIE
ECIE
NRIE
Mnemonic
0
0
0
N/A
0
0
0
0
Reset
Buffer not ready interrupt pending
Set when the DMA channel encounters a buffer descriptor
whose F bit is in the incorrect state. When NRIP is set, the
DMA channel stops until the bit is cleared by firmware; the
DMA channel does not go to the next buffer descriptor.
When NRIP is cleared by firmware, the buffer descriptor is
tried again.
Channel abort interrupt pending
Set when the DMA channel finds that the CA bit is set in
the DMA Control register. When CAIP is set, the DMA
channel stops until the bit is cleared by firmware. The
DMA channel automatically goes to the next buffer
descriptor when CAIP is cleared.
The CA bit in the DMA Control register must be cleared,
using firmware, before CAIP is cleared. Otherwise, the
next buffer descriptor aborts as well.
Premature complete interrupt pending
Set when the DMA channel, configured to operate in fly-by
read mode, receives an end-of-transfer indicator from the
peripheral while processing a DMA buffer descriptor. The
DMA channel goes to the next buffer descriptor.
NCIP is set when PCIP is set, for backward compatibility.
N/A
Premature complete interrupt enable
Normal completion interrupt enable
Error completion interrupt enable
Buffer not ready interrupt enable
Description
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