NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 116

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Burst cycles
1 0 4
S t a t i c m e m o r y ( S R A M ) c o n t r o l l e r
Figure 7: Asynchronous SRAM cycles
The SRAM controller supports both read and write burst cycles. Figure 8 shows a
synchronous SRAM burst read cycle.
ADDR
BCLK
DATA
BEn_
CS0_
CS1_
R/W_
WE_
OE_
TA_
The BE_, OE_, and WE_ signals transition based on the falling edge of BCLK.
–
–
The rising edge of BCLK where TA_ is low defines the last TW cycle. Read
data is sampled and write data is valid on the rising edge of BCLK where TA_
is low.
T1
The BE_, OE_, or WE_ signal transitions low on the first falling edge after
CS[4:0]_ is asserted.
The BE_, OE_, or WE_ signal transitions high on the first falling edge after
TA_ is recognized (TA_ is sampled using the rising edge of BCLK).
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Async Write
TW
*
T2
T1
TW
Async Read
TW
*
T2
T1
Async Write
TW
*
T2