NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 50

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3 8
W o r k i n g w i t h A R M e x c e p t i o n s
Note:
Exception entry/exit summary
In the variable
Table 18: Exception entry/exit by exception type
Notes:
1
2
3
4
BL
RESET
UNDEF
SWI
ABORT P
ABORT D
IRQ
FIRQ
Return/
exception
Where PC is the address of the BL/SWI/undefined instruction fetch that had the
prefetch abort. BL is a branch with link instruction.
Where PC is the address of the instruction that was not executed since FIRQ or
IRQ took priority.
Where PC is the address of the load or store instruction that generated the data
abort.
The value saved in
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
An explicit switch back to Thumb state is never needed. Restoring the
CPSR from the SPSR automatically sets the T bit to the value it held
immediately before the exception.
MOV PC, R14
NA
MOVS PC, R14_und
MOVS PC, R14_svc
SUBS PC, R14_abt, #4
SUBS PC, R14_abt, #8
SUBS PC, R14_irq, #4
SUBS PC, R14_firq, #4
Return instruction
R14_x
,
R14
R14_svc
is the Link register;
upon reset is unpredictable.
PC+4
NA
PC+4
PC+4
PC+4
PC+8
PC+4
PC+4
Previous state
ARM R14_x
_x
is the previous state of the processor.
PC+2
NA
PC+2
PC+2
PC+4
PC+8
PC+4
PC+4
Previous state
Thumb R14_x
1
4
1
1
1
3
2
2
Notes