NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 318

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NS7520 clock speed erratum
3 0 6
N S 7 5 2 0 e r r a t a
When the NS7520 is configured to use the PLL clock generator, the system clock can
come up at 1/2 the configured frequency, or at a higher frequency — usually 64 MHz.
When the PLLTST and BISTEN signals are set high with the SCANEN signal low, the PLL
clock generator should produce the system clock based on the code it reads on
address signals A[4:0]. on occasion, the system clock is either 1/2 the frequency or
greater than the configured frequency due to the internal PLL circuitry not being
properly reset.
Note:
Workaround
Ensure that the RESET source has adequate fall/rise times and is free from glitches
and ringing to prevent 64 MHz or other higher frequencies. This example shows rise
and fall timing:
Invert the active LVTTL RESET_N signal and attach it to the SCANEN_N pin to prevent
the 1/2 BCLK failure. The maximum delay (inverter propagation delay plus the etch
delay) between pins A10 and L13 must be less than 8ns. This next example shows the
SCANEN_N inverter with active TTL monitor:
When the PLL is bypassed, PLLTST_N, BISTEN_N, and SCANEN_N all equal a
logic “1” and this erratum does not apply.
tF max = 18ns
Vin = 2.0V to 0.8V
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
tF
tR max = 18ns
Vin = 0.8V to 2.0V
tR