NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 110

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9 8
M E M m o d u l e c o n f i g u r a t i o n
Table 38: Chip Select Option Register A bit definition
WAIT[3:0]/BCYC[1:0] continued
Bits
Access
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
Mnemonic
Reset
For OE- or WE-controlled cycles, an additional
BCLK cycle is added to each memory cycle.
When DRSEL=0
When DRSEL=1 and DMODE=2’b00
When DRSEL=1 and DMODE=2’b01 at full
speed
Description
RAS_ is always asserted for one BCLK cycle.
RAS_ is always asserted for one BCLK cycle.
cycles in a single access. The first memory
cycle of a burst access follows the timing of a
single access.
for all cycles that follow the initial burst. If
BCYC is set to 0, the controller behaves as if
BCYC is set to 1.
CAS_ is asserted for WAIT+.5 BCLK cycles
in a single access. CAS_ is negated for one
clock cycle between assertions.If WAIT is set
to 0, the controller behaves as if WAIT is set
to 1.
follows the timing of a single access. CAS_ is
asserted BCYC+1 BCLK cycles for all cycles
that follow the initial cycle in a burst. If
BCYC is set to 0, the controller behaves as if
BCYC is set to 1.
CAS_ is asserted for WAIT BCLK cycles in a
single access. CAS_ is bigoted for one clock
cycle between assertions. If WAIT is set to 0,
the controller behaves as if WAIT is set to 1.
CS[4:0]_ is asserted for WAIT+2 BCLK
CS[4:0]_ is asserted BCYC+1 BCLK cycles
The first memory cycle of a burst access