NS7520B-1-I46 Digi International, NS7520B-1-I46 Datasheet - Page 171

• Manufacturer Part Number: NS7520B-1-I46
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-I46

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 53: Ethernet General Control register bit definition
D31
D30
D29
D28
D27
D26
D25
D24
Bits
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
ERX
ERXDMA
ERXLNG
ERXSHT
ERXREG
ERFIFOH
ERXBR
ERXBAD
Mnemonic
0
0
0
0
0
0
0
0
Reset
Enable receive FIFO
0
1
Set to 1 to allow data to be received from the MAC
receiver.
Set to 0 (clear) to reset the receive side FIFO.
Enable receive DMA
0
1
Set to 1 to allow the EFE module to issue receive data move
requests to the DMA controller.
Clear this bit to temporarily stall receive side Ethernet
DMA.
Accept long (>1520 bytes [MAXF setting]) receive
packets
When set to 1, allows the MAC to accept packets that are
larger than 1520 bytes.
Accept short (<60 bytes) receive packets
When set to 1, allows the MAC to accept packets that are
smaller than 60 bytes.
The ERXSHT bit is used primarily for debugging.
Enable Receive Data register ready interrupt
Set to 1 to generate an interrupt when data is available in
the RX FIFO.
Enable receive data FIFO half full interrupt
Set to 1 to generate an interrupt when the RX FIFO is at
least half full (1024 bytes).
Enable receive buffer ready interrupt
Set to 1 to generate an interrupt when a new data packet is
available in the RX FIFO.
Accept bad receive packets
When set to 1, allows the MAC to accept packets received
in error. Bad receive packets include those packets with
CRC errors, alignment errors, and dribble errors.
The ERXBAD bit is used primarily for debugging.
Description
w w w . d i g i e m b e d d e d . c o m
Disables inbound data flow and resets the FIFO
Enables inbound data flow
Disables inbound DMA data request
Enables inbound DMA data request
E t h e r n e t M o d u l e
1 5 9