PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet
PEF 20525 F V1.3
Specifications of PEF 20525 F V1.3
PEF20525FV13XP
SP000007592
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PEF 20525 F V1.3 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... Chapter "Electrical Characteristics" updated with final characterization results. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at 2000-09-14 PASSAT V1.1 Preliminary Data Sheet, 09.99, DS2 http://www.infineon.com ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.2.13.1 NRZ and NRZI Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.2.3 Channel Specific DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 5.2.4 Miscellaneous ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 43 HDLC Receive Data Processing in Address Mode Figure 44 HDLC Receive Data Processing in Address Mode ...
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List of Tables Table 1 Microprocessor Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 ...
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List of Registers Register 1 GCMDR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Registers Register 43 RTSA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Registers Register 85 VER0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Preface The 2 Channel Serial Optimized Communication Controller for HDLC/PPP PEB 20525 (SEROCCO- Protocol Controller for a wide range of data communication and telecommunication applications. information on hardware and software related issues as well as on general operation. ...
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Your Comments We welcome your comments on this document. We are continuously trying improving our documentation. Please send your remarks and suggestions by e-mail to sc.docu_comments@infineon.com Please provide in the subject of your e-mail: device name (SEROCCO-H), device number (PEB ...
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Introduction The SEROCCO Serial Communication Controller with two independent serial 1) channels . The serial channels are derived from updated protocol logic of the ESCC and DSCC4 device family providing a large set of protocol support and ...
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Channel Serial Optimized Communication Controller for HDLC/PPP SEROCCO-H Version 1.2 1.1 Features Serial communication controllers (SCCs) • Two independent channels • Full duplex data rates on each channel 12.5 Mbit/s sync - 2 Mbit/s with DPLL ...
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CRC generation and checking (CRC-CCITT or CRC-32) – Transparent CRC option per channel and/or per frame – Programmable Preamble (8 bit) with selectable repetition rate – Error detection (abort, long frame, CRC error, short frames) • Bit Synchronous PPP ...
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Microprocessor Interface • 8-bit bus interface (P-LFBGA-80-2 package) • 8/16-bit bus interface (P-TQFP-100-3 package) • Multiplexed and De-multiplexed address/data bus • Intel/Motorola style • Asynchronous interface • Maskable interrupts for each channel General Purpose Port (GPP) Pins ( ...
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Logic Symbol A(7:0) 1) ALE 3) D(15:8) D(7: BHE Microprocessor 2) LDS Interface 2) 3) UDS 2) R/W DTACK CS INT/INT CLK RESET 1) Intel bus mode 2) Motorola bus mode 3) 16-bit ...
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Typical Applications SEROCCO-H devices can be used in LAN-WAN inter-networking applications such as Routers, Switches and Trunk cards and support the common V.35, ISDN BRI (S/T) and RFC1662 standards. Its new features provide powerful hardware and software interfaces to ...
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CPU RAM Bank Figure 3 System Integration With External DMA Controller Data Sheet Transceiver, Framer . . . SEROCCO-H PEB 20525 PEF 20525 . . . System Bus DMA Controller 22 PEB 20525 PEF 20525 Introduction 2000-09-14 ...
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Serial Configuration Examples SEROCCO-H supports a variety of serial configurations at Layer-1 and Layer-2 level. The outstanding variety of clock modes supporting a large number of combinations of external and internal clock sources allows easy integration in application environments. ...
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RxD CxD TxD Slave Figure 5 Point-to-Multipoint Bus Configuration . . . RxD CxD TxD Master 1 SEROCCO-H PEB 20525 PEF 20525 . . . Figure 6 Multimaster Bus Configuration Data Sheet . ...
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Differences between SEROCCO-H and the HSCX/ESCC Family This chapter is useful for all being familiar with the HSCX/ESCC family. 1.4.1 Enhancements to the HSCX Serial Core The SEROCCO-H SCC cores contain the core logic of the HSCX as the ...
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Pin Descriptions 2.1 Pin Diagram P-LFBGA-80-2 (top view) RD# VSS READY# TMS DTACK# VDD WR# D2 VSS VSS TEST2 D7 VSS VDD DRTA DRRA 9 8 Figure 7 Pin Configuration P-LFBGA-80-2 Package Data Sheet P-LFBGA-80-2 A0/ ...
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Pin Diagram P-TQFP-100-3 (top view) P-TQFP-100-3 VDD VSS D12 D13 D14 80 D15 VDD VSS DRTA DACKA# 85 DRRA DRRB/GP1 DRTB/GP0 DACKB#/GP2 RTSB# 90 RxDB VDD VSS RxCLKB TxDB 95 TxCLKB CDB/FSCB/RCGB#/OSRB VDD TRST# TDI 100 Figure 8 Pin ...
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Pin Definitions and Functions Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 D15 - 80 D14 - 79 D13 - 78 D12 - 75 D11 - 74 D10 - 73 ...
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Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 BLE UDS ALE Data Sheet Function Out (O) I Address Line A0 (8-bit modes) In Motorola and in Intel ...
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Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 BHE LDS R Data Sheet Function Out (O) I Data Strobe (8-bit Motorola bus ...
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Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 WIDTH G7 55 CLK H1 20 INT/INT O Data Sheet Function Out (O) I Write Strobe (Intel bus mode only) ...
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Table 1 Microprocessor Bus Interface Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 READY DTACK H2 19 RESET I Data Sheet Function Out (O) O Ready (Intel bus mode) O Data Transfer Acknowledge (Motorola mode) During ...
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Table 2 External DMA Interface Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 DRTA A8 86 DRRA B7 85 DACKA I Data Sheet Function Out (O) O DMA Request Transmitter Channel A The transmitter on a ...
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Table 2 External DMA Interface Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 DRTB GP0 C7 87 DRRB GP1 C6 89 DACKB GP2 Data Sheet Function Out (O) O DMA Request Transmitter Channel B (corresponding to ...
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Table 3 Serial Port Pins Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 TxCLK RxCLK A Data Sheet Function Out (O) I/O Transmit Clock Channel A The function of this pin depends on ...
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Table 3 Serial Port Pins (cont’d) Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 CDA FSCA RCGA OSRA Data Sheet Function Out (O) I Carrier Detect Channel A The function of this pin depends on the ...
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Table 3 Serial Port Pins (cont’d) Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 RTSA E2 10 CTSA CxDA TCGA OSTA Data Sheet Function Out (O) O Request to Send Channel A The function of this ...
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Table 3 Serial Port Pins (cont’d) Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 TxDA E1 12 RxDA A4 96 TxCLK RxCLK CDB FSCB RCGB OSRB A6 90 RTSB C1 ...
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Table 3 Serial Port Pins (cont’d) Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 RxDB D3 8 XTAL1 E4 7 XTAL2 Table 4 General Purpose Pins Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80-2 ...
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Table 5 Test Interface Pins Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80 TRST C2 2 TCK A2 100 TDI A1 1 TDO H8 46 TMS D7 68 TEST1 C9 69 TEST2 Data Sheet Function Out ...
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Table 6 Power Pins Pin No. Symbol In (I) P- P-TQFP- LFBGA- 100-3 80-2 A7, B1, 3, 15, V DD3 B8, C4, 21, 27, C5, E7, 35, 40, F1, G4, 47, 49, G9, H6, 56, 62, J1 70, 76, 82, ...
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Functional Overview The functional blocks of SEROCCO-H can be divided into two major domains: – the microprocessor interface of SEROCCO-H provides access to on-chip registers and to the "user" portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally these ...
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Serial Communication Controller (SCC) 3.2.1 Protocol Modes Overview The SCC is a multi-protocol communication controller. The core logic provides different protocol modes which are listed below: • HDLC Modes – HDLC Transparent Operation (Address Mode 0) – HDLC Address ...
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Figure 10 SCC Transmit FIFO A 32 bytes FIFO part is accessable by the CPU/DMA controller; it accepts transmit data even if the SCC is in power-down condition (register The only exception is a transmit data underrun (XDU) event. In ...
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Figure 11 SCC Receive FIFO New receive data is announced to the CPU with an interrupt latest when the FIFO fill level reaches a chosen threshold level (selected with bitfield ’RFTH(1..0)’ in register “CCR3H” on Page 153). Default value for ...
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SCC FIFO Access Figure 12 and Figure 13 accesses to the transmit and receive FIFOs. XFIFO . Byte Byte Byte Byte ...
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Clocking System The SEROCCO-H includes an internal Oscillator (OSC) as well as two independent Baud Rate Generators (BRG) and two Digital Phase Locked Loop (DPLL) circuits. The transmit and receive clock can be generated either • externally, and supplied ...
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The internal structure of each SCC channel consists of a transmit protocol machine clocked with the transmit frequency f receive frequency f . REC The clocks f and f TRM REC clock inputs e.g. f and TxCLK input pin. TRM ...
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The last column describes the function of signal TxCLK which in some clock modes can be enabled as output signal monitoring the effective transmit clock or providing a time slot control signal (clock mode 5). ...
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The clocking concept is illustrated in a block diagram manner in the following figure: Additional control signals are not illustrated (please refer to the detailed clock mode descriptions below). settings controlled by: register CCR0, bit field 'CM' selects the clock ...
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Clock Modes 3.2.3.1 Clock Mode 0 (0a/0b) Separate, externally generated receive and transmit clocks are supplied to the SCC via their respective pins. The transmit clock may be directly supplied by pin TxCLK (clock mode 0a) or generated by the ...
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Clock Mode 1 Externally generated RxCLK is supplied to both the receiver and transmitter. In addition, a receive strobe can be connected via CD and a transmit strobe via TxCLK pin. These strobe signals work on a per bit ...
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Clock Mode 2 (2a/2b) The BRG is driven by an external clock (RxCLK pin) and delivers a reference clock for the DPLL which is 16 times of the resulting DPLL output frequency which in turn supplies the internal receive ...
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Clock Mode 3 (3a/3b) The BRG is fed with an externally generated clock via pin RxCLK. Depending on the value of bit ’SSEL’ in register DPLL which is 16 times of the resulting DPLL output frequency (clock mode 3a) ...
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Clock Mode 4 Separate, externally generated receive and transmit clocks are supplied via pins RxCLK and TxCLK. In addition separate receive and transmit clock gating signals are supplied via pins RCG and TCG. These gating signals work on a ...
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Clock Mode 5a (Time Slot Mode) This operation mode has been designed for application in time-slot oriented PCM systems. Note: For correct operation NRZ data coding/encoding should be used. The receive and transmit clock are common for each channel ...
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TTSA0..3: Transmit Time Slot Assignment Register TTSA3 7 FSC RxCLK active time slot TS delay (transmit TTSN*8 + TCS (1...1024) TS delay (receive RTSN*8 + RCS (1...1024) RTSA0..3: Receive Time Slot Assignment Register RTSA3 7 Figure ...
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Note: If time-slot selected, the DELAY has long as the PCM frame itself to achieve synchronization (at least for the 2nd and subsequent PCM frames): DELAY = PCM frame length = 1 + ...
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TTSA0..3: Transmit Time Slot Assignment Register TTSA3 7 0 PCMTX0..3: Transmit PCM Mask Register PCMTX3 FSC ... RxCLK active time slot TS delay (transmit TTSN*8 + TCS (1..1024) TS delay (receive RTSN*8 + ...
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Time Slot Assigner (TSA) Ctrl RxCLK FSC internal tx strobe TxCLK TS-Control TxD internal rx strobe RxD Figure 22 Clock Mode 5a Configuration Note: The transmit time slot delay and width is programmable via bit ...
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The following figures provide a more detailed description of the TSA internal counter operation and exceptional cases: clock mode 5a bit TSCM='0' (continuous mode) FSC RxCLK, ... TxCLK ffs ...
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Each frame sync pulse starts the internal offset counter with (1024 - TSdelay) whereas TSdelay is the configured value defining the start position. Whenever the offset counter reaches its maximum value 1024, it triggers the duration counter to start operation. ...
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Clock Mode 5b (Octet Sync Mode) This operation mode has been designed for applications using Octet Synchronous PPP based on clock mode 5a, but only 8-bit (octet) wide time slot operation is supported, i.e. bits TTSA1.TEPCM and ...
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TTSA0..3: Transmit Time Slot Assignment Register TTSA3 7 PCMTX0..3: Transmit PCM Mask Register PCMTX3 31 OSR OST RxCLK ... TxCLK active time slot TS delay (transmit TTSN*8 + TCS (1...1024) TS delay (receive RTSN*8 + RCS ...
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Time Slot Assigner (RTSA) Time Slot Assigner Ctrl RxCLK TxCLK OSR OST internal tx strobe TxD internal rx strobe RxD Figure 26 Clock Mode 5b Configuration Note: The transmit time slot delay and width is ...
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Clock Mode 6 (6a/6b) This clock mode is identical to clock mode 2a/2b except that the clock source of the BRG is supplied at pin XTAL1. The BRG is driven by the internal oscillator and delivers a reference clock ...
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Clock Mode 7 (7a/7b) This clock mode is identical to clock mode 3a/3b except that the clock source of the BRG is supplied at pin XTAL1. The BRG is driven by the internal oscillator. Depending on the value of ...
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Baud Rate Generator (BRG) Each serial channel provides a baud rate generator (BRG) whose division factor is controlled by registers BRRL depends on the selected clock mode. Table 9 BRRL/BRRH Register and Bit-Fields Register Bit-Fields Offset Pos. Name BRRL ...
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Interference Rejection and Spike Filtering Two or more edges in the same directional data stream within a time period of 16 reference clocks are considered to be interference and consequently no additional clock adjustment is performed. Phase Adjustment (PA) Referring ...
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DPLL 0 Count 0 Correction DPLL Output Figure 29 DPLL Algorithm (NRZ and NRZI Encoding, Phase Shift Enabled) DPLL Count 0 Correction DPLL Output ...
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DPLL Count 0 +PA Correction Transmit Clock Receive Clock Figure 31 DPLL Algorithm for FM0, FM1 and Manchester Encoding To supervise correct function when ...
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SCC Serial Bus Configuration Mode Beside the point-to-point configuration, the SCC effectively supports point-to-multipoint (pt-mpt, or bus) configurations by means of internal idle and collision detection/collision resolution methods pt-mpt configuration, comprising a central station (master) and several ...
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HDLC/SDLC: Transmission will be initiated again by the SCC as soon as possible if the first part of the frame is still present in the SCC transmit FIFO. If not, an XMR interrupt is generated. Since a ‘zero’ (‘low’) on ...
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Serial Bus Configuration Timing Modes If a bus configuration has been selected, the SCC provides two timing modes, differing in the time interval between sending data and evaluation of the transmitted data for collision detection. • Timing mode 1 ...
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Manchester (also known as Bi-Phase) The desired line coding scheme can be selected via bit field ’SC(2:0)’ in register CCR0H. 3.2.13.1 NRZ and NRZI Encoding NRZ: The signal level corresponds to the value of the data bit. By programming ...
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Transmit Clock Receive Clock FM0 FM1 1 Figure 34 FM0 and FM1 Data Encoding 3.2.13.3 Manchester Encoding Manchester: In the first half of the bit cell, the physical signal level corresponds to the logical value of the data bit. At ...
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Modem Control Signals (RTS, CTS, CD) 3.2.14.1 RTS/CTS Handshaking The SCC provides two pins (RTS, CTS) per serial channel supporting the standard request-to-send modem handshaking procedure for transmission control. A transmit request will be indicated by outputting logical ‘0’ ...
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TxCLK TxD RTS CTS Figure 36 RTS/CTS Handshaking Beyond this standard RTS function, signifying a transmission request of a frame (Request To Send), in HDLC mode the RTS output may be programmed for a special function via SOC1, SOC0 bits ...
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RxD) are connected, generating a local loopback result, the user can perform a self-test of the SCC. SCC receive logic SCC transmit logic Figure 37 SCC Test Loop Transmit data can be disconnected from pin TxD by setting ...
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Table 10 Data Bus Access 16-bit Intel Mode BHE BLE Register Access 0 0 Word access (16 bit Byte access (8 bit), odd address 1 0 Byte access (8 bit), even address data transfer Table ...
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Interrupt Architecture For certain events in SEROCCO-H an interrupt can be generated, requesting the CPU to read status information from SEROCCO-H. The interrupt line INT/INT is asserted with the output characteristics programmed in bit field ’IPC(1..0)’ in register Page ...
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The Global Interrupt Status Register (GSTAR) serves as pointer to pending channel related interrupts and general purpose port interrupts. 3.6 General Purpose Port Pins 3.6.1 GPP Functional Description General purpose port pins are provided on pins GP6, GP8, GP9 and ...
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Detailed Protocol Description The following Table 12 provides an overview of all supported protocol modes and . The desired protocol mode is selected via bit fields in the channel configuration registers CCR2L and CCR3L. Table 12 Protocol Mode Overview ...
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Table 13 Address Comparison Overview Mode Address Field 16 bit FE FE Address Mode 2 - Auto Mode 8 bit Address 8 bit FE Mode 1 Address None Mode 0 4.1.0.1 Automode Characteristics: Window size 1, random message length, address ...
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HDLC frames with address fields that do not match any of the address combinations, are ignored by the SCC. In the case of a 1-byte address, only According to the X.25 LAPB ...
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ADDR FLAG (high) to RFIFO registers RAH1,2 RAL1,2 involved Figure 39 HDLC Receive Data Processing in 16 bit Automode 8 bit ADDR FLAG (low) to RFIFO opt. 1) registers RAL1,2 involved (address compare) Figure 40 HDLC Receive Data ...
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ADDR FLAG (low) to RFIFO opt. 1) registers RAL1,2 involved (address compare) Figure 42 HDLC Receive Data Processing in Address Mode 2 (8 bit) 8 bit ADDR 16 bit ADDR FLAG to RFIFO opt. 1) registers RAH1,2 involved ...
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Receive Address Handling The Receive Address Low/High Bytes (registers masked on a per bit basis by setting the corresponding bits in the mask registers AMRAL1/AMRAH1 and AMRAL2/AMRAH2. This allows extended broadcast address recognition. Masked bit positions always match in ...
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Frames with automatic bit Address and Control Byte Generation (Automode): 8 bit ADDR 16 bitADDR FLAG XFIFO registers XAD1 involved Frames without automatic Address and Control Byte Generation (Address Mode 2/1/0): FLAG XFIFO option 2) Generation of ...
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Note: The SCC does not check whether the length of the frame, i.e. the number of bytes transmitted makes sense according the HDLC protocol or not. 4.1.4 Shared Flags If the ‘Shared Flag’ feature is enabled by setting ...
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In standard applications, CRC-CCITT algorithm is used. The Frame Check Sequence at the end of each frame consists of two bytes of CRC checksum. If required, the CRC-CCITT algorithm can be replaced by the CRC-32 algorithm, enabled via bit ’C32’ ...
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Additionally an optional ’FLEX’ interrupt is generated prior to ’RME’, indicating that the maximum receive frame length was exceeded. Receive operation continues with the beginning of the next receive frame. 4.2 Point-to-Point Protocol (PPP) Modes PPP (as described in RFC1662) ...
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Data Transparency in PPP Mode When transporting bit-files (as opposed to text files), or compressed files, the characters could easily represent MODEM control characters (such as CTRL-Q, CTRL-S) which the MODEM would not pass through. SEROCCO-H maintains an Async ...
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ACCM0..3: Async Control Character Map Register ACCM3 ... 0 0 ... UDAC0..3: User Defined Async Control Character Map Register 7 UDAC3 7Eh data in transmit FIFO: HDLC framing PPP mapping serial line received ...
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Extended Transparent Mode Characteristics: fully transparent When programmed in the extended transparent mode via the MDS1, MDS0, ADM = ‘111’), the SCC performs fully transparent data transmission and reception without HDLC framing, i.e. without • FLAG insertion and deletion ...
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Full-Duplex LAPB/LAPD Operation Initially (i.e. after RESET), the LAP controllers of the two serial channels are configured to function as a combined (primary/secondary) station, where they autonomously perform a subset of the balanced X.25 LAPB/ISDN LAPD protocol. Reception of ...
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RR , REJ SREJ , Y CRC Error or Abort ? N Y Prot. Error ? N Int PCE : RESET RRNR 1 Wait for N Acknowledge ? Y N N(R)=V (S)+ (S) +1 (S) ...
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Transmission of Frames: The SCC autonomously transmits S commands and S responses in the auto mode. Either transparent or I-frames can be transmitted by the user. The software timer has to be operated in the internal timer mode to transmit ...
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Rec. RNR Set RRNR 1 t Run Out n1-1 Load Rec. Ready ? Y Trm RR Trm RNR Command p=1 Command p=1 , ...
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Examples The interaction between SCC and the host during transmission and reception of I-frames is illustrated in the following two figures. The flow control with RR/RNR of I-frames during transmission/reception is illustrated in and protocol errors are shown in I ...
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Protocol Error Handling: Depending on the error type, erroneous frames are handled according to Table 14 Error Handling Frame Type Error Type I CRC error Aborted Unexpected N(S) Unexpected N(R) S CRC error Aborted Unexpected N(R) With I-field Note: The ...
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Note: The broadcast address may be programmed in register required. In this case registers The primary station has to operate in transparent HDLC mode. Reception of Frames: The reception of frames functions similarly to the LAPB/LAPD operation (see Duplex LAPB/LAPD ...
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RR(0)p=1 RR(0)f=1 Secondary Figure 51 No Data to Send: Data Reception/Transmission XIF RR(0)p=1 RR(1)p=0 ALLS Figure 52 Data Transmission (without error), Data Transmission (with error) 4.4.3 Signaling System #7 (SS7) Operation The SEROCCO-H supports the signaling system #7 (SS7) which ...
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Receive The SS7 protocol is supported by the following hardware features in receive direction: • Recognition of Signaling Unit type • Discard of repeatedly received FISUs and optionally of LSSUs if content is unchanged • Check if the length of ...
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FISUs continues. The internally generated FISUs contain FSN and BSN of the last transmitted signaling unit written to XFIFO. Using CMDRL.XREP=’1’, the contents of XFIFO (1..32 bytes) can be sent continuously. This cyclic transmission can be stopped with ...
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Register Description 5.1 Register Overview The SEROCCO-H global registers are used to configure and control the Serial Communication Controllers (SCCs), General Purpose Pins (GPP) and DMA operation. All registers are 8-bit organized registers, but grouped and optimized for 16 ...
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Table 15 Register Overview (cont’d) Offset Ch Register A B read write 12 62 STARL STARH CMDRL CMDRH CCR0L CCR0H ...
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Table 15 Register Overview (cont’d) Offset Ch Register A B read write 27 77 UDAC3 TTSA0 TTSA1 TTSA2 TTSA3 RTSA0 ...
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Table 15 Register Overview (cont’d) Offset Ch Register A B read write 44 94 AMRAL1 AMRAH1 AMRAL2 AMRAH2 RLCRL RLCRH ...
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Table 15 Register Overview (cont’d) Offset Ch Register A B read write ... Reserved RMBSL RMBSH RBCL RBCH ...
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Detailed Register Description 5.2.1 Global Registers Each register description is organized in three parts: • a head with general information about reset value, access type (read/write), offset address and usual handling; • a table containing the bit information (name ...
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Register 2 GMODE Global Mode Register CPU Accessibility: read/write Reset Value Offset Address typical usage: written by CPU evaluated by SEROCCO-H Bit EDMA EDMA Enable External DMA Support This bit field controls the ...
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OSCPD Oscillator Power Down Setting this bit to ’0’ enables the internal oscillator. For power saving purposes (escpecially if clock modes are used which do not need the internal oscillator) this bit may remain set to ’1’. OSCPD=’0’ OSCPD=’1’ Note: ...
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Register 3 GSTAR Global Status Register CPU Accessibility: read only Reset Value Offset Address typical usage: written by SEROCCO-H evaluated by CPU Bit 7 6 GPI DMI GPI General Purpose Port Indication This bit indicates, that ...
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ISA2 Channel A Interrupt Status Register 2 ISA1 Channel A Interrupt Status Register 1 ISA0 Channel A Interrupt Status Register 0 ISB2 Channel B Interrupt Status Register 2 ISB1 Channel B Interrupt Status Register 1 ISB0 Channel B Interrupt Status ...
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Register 4 GPDIRL GPP Direction Register (Low Byte) CPU Accessibility: read/write Reset Value Offset Address typical usage: written by CPU, evaluated by SEROCCO-H Bit Register 5 GPDIRH GPP Direction Register (High Byte) ...
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GPnDIR GPP Pin n Direction Control This bit selects between input and output function of the corresponding GPP pin: bit = ’0’ bit = ’1’ Data Sheet Register Description (GPDIRH) output input (reset value) 5-117 PEB 20525 PEF 20525 (-) ...
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Register 6 GPDATL GPP Data Register (Low Byte) CPU Accessibility: read/write Reset Value: - Offset Address typical usage: written by CPU(outputs) and SEROCCO-H(inputs), evaluated by SEROCCO-H(outputs) and CPU(inputs) Bit Register 7 GPDATH GPP Data ...
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GPnDAT GPP Pin n Data I/O Value This bit indicates the value of the corresponding GPP pin: bit = ’0’ bit = ’1’ Data Sheet Register Description (GPDATH) If direction is input: input level is ’low’; if direction is output: ...
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Register 8 GPIML GPP Interrupt Mask Register (Low Byte) CPU Accessibility: read/write Reset Value Offset Address typical usage: written by CPU, evaluated by SEROCCO-H Bit Register 9 GPIMH GPP Interrupt Mask Register ...
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GPnIM GPP Pin n Interrupt Mask This bit controls the interrupt mask of the corresponding GPP pin: bit = ’0’ bit = ’1’ Data Sheet Interrupt generation is enabled. An interrupt is generated on any state transition of the corresponding ...
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Register 10 GPISL GPP Interrupt Status Register (Low Byte) CPU Accessibility: read only Reset Value Offset Address typical usage: written by SEROCCO-H, read and evaluated by CPU Bit Register 11 GPISH GPP ...
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GPnI GPP Pin n Interrupt Indiction This bit indicates if an interrupt event occured on the corresponding GPP pin: bit = ’0’ bit = ’1’ Data Sheet No interrupt indication is pending at this pin (no state transition has occured). ...
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Register 12 DCMDR DMA Command Register CPU Accessibility: read/write Reset Value Offset Address typical usage: written by CPU, evaluated by SEROCCO-H Bit 7 6 RDTB 0 RDTB Reset DMA Transmit Channel B RDRB Reset DMA Receive ...
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Register 13 DISR DMA Interrupt Status Register CPU Accessibility: read only Reset Value Offset Address typical usage: written by SEROCCO-H, evaluated by CPU Bit RBFB Note: Interrupt indications are stored even if masked ...
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TDTEB Transmit DMA Transfer End Channel B TDTEA Transmit DMA Transfer End Channel A This bit set to ’1’ indicates that the data is completely moved from the transmit buffer to the on-chip transmit FIFO, i.e. the transmit byte count ...
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Register 14 DIMR DMA Interrupt Mask Register CPU Accessibility: read/write Reset Value Offset Address typical usage: Bit MRBFB MRBFB Mask Receive Buffer Full Interrupt Channel B MRBFA Mask Receive Buffer Full Interrupt Channel ...
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Channel Specific SCC Registers Each register description is organized in three parts: • a head with general information about reset value, access type (read/write), channel specific offset addresses and usual handling; • a table containing the bit information (name ...
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Receive FIFO (RFIFO) Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) accesses, depending on the selected microprocessor bus width using signal ’WIDTH’. In 16-bit bus mode only 16-bit accesses to RFIFO are allowed. Only ...
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XTF command. The address provided during an XFIFO write access is not incremental always 10 for channel • DMA Controlled Data Transfer (GMODE.EDMA=’1’) If DMA operation is enabled, the SEROCCO-H autonomously requests data transfer ...
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Register 17 STARL Status Register (Low Byte) CPU Accessibility: read only Reset Value Channel A Offset Address typical usage: updated by SEROCCO-H read and evaluated by CPU Bit 7 6 Command Status XREPE 0 Register 18 ...
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XREPE Transmit Repetition Executing XREPE=’0’ XREPE=’1’ CEC Command Executing CEC=’0’ CEC=’1’ Note: CEC will stay active if the SCC is in power-down mode serial clock, needed for command execution, is available. XDOV Transmit FIFO Data Overflow XDOV=’0’ ...
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CD CD (Carrier Detect) Input Signal State CD=’0’ CD=’1’ Note: Optionally this input can be programmed to generate an interrupt on signal level changes. RLI Receive Line Inactive This bit indicates that neither flags as interframe time fill nor data ...
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XRNR Transmit RNR Status This status bit is significant in Automode only. It indicates the receiver status of the local station (SCC). XRNR=’0’ XRNR=’1’ RRNR Received RNR (Receiver Not Ready) Status This status bit is significant in Automode only. It ...
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Register 19 CMDRL Command Register (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU, evaluated by SEROCCO-H Bit 7 6 Timer STI TRES Register 20 CMDRH Command Register (High ...
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STI Start Timer Command Self-clearing command bit: HDLC Automode: In HDLC Automode the timer is used internally for the autonomous protocol support functions. The timer is started automatically by the SCC when an I-Frame is sent out and needs to ...
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XRES Transmitter Reset Command Self-clearing command bit: XRES=’1’ XF Transmit Frame This self-clearing command bit is significant in interrupt driven operation only (GMODE.EDMA=’0’). XF=’1’ XME Transmit Message End Self-clearing command bit: XME=’1’ XREP Transmission Repeat Command Self-clearing command bit: XREP=’1’ ...
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RMC Receive Message Complete Self-clearing command bit: RMC=’1’ RNR Receiver Not Ready Command NON self-clearing command bit: This command bit is significant in HDLC Automode only. RNR=’0’ RNR=’1’ RSUC Reset Signaling Unit Counter Self-clearing command bit: This command bit is ...
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Register 21 CCR0L Channel Configuration Register 0 (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 misc. VIS PSD Register 22 ...
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VIS Masked Interrupts Visible VIS=’0’ VIS=’1’ Note: Interrupts masked in registers interrupt. PSD DPLL Phase Shift Disable This option is only applicable in the case of NRZ or NRZI line encoding is selected. PSD=’0’ PSD=’1’ TOE Transmit Clock Out Enable ...
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CM(2:0) Clock Mode This bit field selects one of main clock modes 0..7. For a detailed description of the clock modes refer ’000’ ’001’ ’010’ ’011’ ’100’ ...
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This bit field selects the line coding of the serial port. Note, that special operation modes and settings may require or exclude operation in special line coding modes. Refer to the ’prerequisites’ in the dedicated mode descriptions ’000’ ...
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Register 23 CCR1L Channel Configuration Register 1 (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 CRL C32 Register 24 CCR1H ...
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CRL CRC Reset Value This bit defines the initial value of the internal transmit/receive CRC generators: CRL=’0’ CRL=’1’ C32 CRC 32 Select This bit enables 32-bit CRC operation for transmit and receive. C32=’0’ C32=’1’ Note: The internal ’valid frame’ criteria ...
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DIV Data Inversion This bit is only valid if NRZ data encoding is selected via bit field SC(2:0) in register CCR0H. DIV=’0’ DIV=’1’ ODS Output Driver Select The transmit data output pin TxD can be configured as push/pull or open ...
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FRTS Flow Control (using signal RTS) Bit ’FRTS’ together with bit ’RTS’ determine the function of signal RTS: RTS, FRTS FCTS Flow Control (using signal CTS) This bit controls the function of ...
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TSCM Time Slot Control Mode This bit controls internal counter operation in time slot oriented clock mode 5: TSCM=’0’ TSCM=’1’ Data Sheet The internal counter keeps running, restarting with zero after being expired. The internal counter stops at its maximum ...
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Register 25 CCR2L Channel Configuration Register 2 (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 MDS(1:0) Register 26 CCR2H Channel ...
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MDS(1:0) Mode Select This bit field selects the HDLC protocol sub-mode including the ’extended transparent mode’. MDS = ’00’ MDS = ’01’ MDS = ’10’ MDS = ’11’ Note: ’MDS(1:0)’ must be set to ’10’ if any PPP mode is ...
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PPPM(1:0) PPP Mode Select This bit field enables and selects the HDLC PPP protocol modes: PPPM = ’00’ No PPP protocol operation. The HDLC sub-mode is PPPM = ’01’ Octet synchronous PPP protocol operation. PPPM = ’10’ Reserved PPPM = ...
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MCS Modulo Count Select This bit is valid in HDLC Automode operation only and determines the control field format: MCS = ’0’ MCS = ’1’ EPT Enable Preamble Transmission This bit enables preamble transmission. The preamble is started after interframe ...
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OIN One Insertion In HDLC mode a one-insertion mechanism similar to the zero-insertion can be activated: OIN=’0’ OIN=’1’ XCRC Transmit CRC Checking Mode XCRC=’0’ XCRC=’1’ Data Sheet The ’1’ insertion mechanism is disabled. In transmit direction a logical ’1’ is ...
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Register 27 CCR3L Channel Configuration Register 3 (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 ELC AFX Register 28 CCR3H ...
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ELC Enable Length Check This bit is only valid in HDLC SS7 mode: If the number of received octets exceeds 272 + 7 within one Signaling Unit, reception is aborted and bit RSTA.RAB is set. ELC=’0’ ELC=’1’ AFX Automatic FISU ...
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RAC Receiver active Switches the receiver between operational/inoperational states: RAC=’0’ RAC=’1’ ESS7 Enable SS7 Mode This bit is only valid in HDLC mode only. ESS7=’0’ ESS7=’1’ Note: If SS7 mode is enabled, ’Address Mode 0’ must be selected by setting ...
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RADD Receive Address Forward to RFIFO This bit is only valid – HDLC sub-mode with address field support is selected (Automode, Address Mode 2, Address Mode 1) – in SS7 mode RADD=’0’ RADD=’1’ RFTH(1:0) Receive FIFO Threshold This ...
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Register 29 PREAMB Preamble Register CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 PRE(7:0) Preamble This bit field determines the preamble pattern ...
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Register 30 ACCM0 PPP ASYNC Control Character Map 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit Register 31 ACCM1 ...
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Register 32 ACCM2 PPP ASYNC Control Character Map2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit Register 33 ACCM3 PPP ...
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ACCM ASYNC Character Control Map This bit field is valid in HDLC octet-synchronous PPP mode only: Each bit selects the corresponding character (indicated as hex value 1F ..00 in the register description table) as control character which has H H ...
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Register 34 UDAC0 User Defined PPP ASYNC Control Character Map 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 35 UDAC1 ...
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Register 36 UDAC2 User Defined PPP ASYNC Control Character Map 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 37 UDAC3 ...
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AC3..0 User Defined ASYNC Character Control Map This bit field is valid in HDLC octet-synchronous PPP mode only: These bit fields define user determined characters as control characters which have to be mapped into the transmit data stream. In register ...
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Register 38 TTSA0 Transmit Time Slot Assignment Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit Register 39 TTSA1 ...
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Register 40 TTSA2 Transmit Time Slot Assignment Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 41 TTSA3 Transmit Time ...
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The following register bit fields allow flexible assignment of bit- or octet-aligned transmit time-slots to the serial channel. For more detailed information refer to chapters Mode 5a (Time Slot Mode)” on Page 56 on Page 63. TCS(2:0) Transmit Clock Shift ...
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Register 42 RTSA0 Receive Time Slot Assignment Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit Register 43 RTSA1 ...
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Register 44 RTSA2 Receive Time Slot Assignment Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 45 RTSA3 Receive Time ...
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The following register bit fields allow flexible assignment of bit- or octet-aligned receive time-slots to the serial channel. For more detailed information refer to chapters Mode 5a (Time Slot Mode)” on Page 56 on Page 63. RCS(2:0) Receive Clock Shift ...
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Register 46 PCMTX0 PCM Mask Transmit Direction Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 T07 T06 Register 47 PCMTX1 ...
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Register 48 PCMTX2 PCM Mask Transmit Direction Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 T23 T22 Register 49 PCMTX3 ...
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PCMTX PCM Mask for Transmit Direction This bit field is valid in clock mode 5 only and the PCM mask must be enabled via bit ’TEPCM’ in register TTSA1. Each bit selects one of 32 (8-bit) transmit time-slots. The offset ...
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Register 50 PCMRX0 PCM Mask Receive Direction Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 R07 R06 Register 51 PCMRX1 ...
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Register 52 PCMRX2 PCM Mask Receive Direction Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 R23 R22 Register 53 PCMRX3 ...
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PCMRX PCM Mask for Receive Direction This bit field is valid in clock mode 5 only and the PCM mask must be enabled via bit ’REPCM’ in register RTSA1. Each bit selects one of 32 (8-bit) receive time-slots. The offset ...
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Register 54 BRRL Baud Rate Register (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit Register 55 BRRH Baud ...
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BRM(3:0) Baud Rate Factor ’M’ BRN(5:0) Baud Rate Factor ’N’ These bit fields determine the division factor of the internal baud rate generator. The baud rate generator input clock and the usage of baud rate generator output depends on the ...
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Register 56 TIMR0 Timer Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 57 TIMR1 Timer Register 1 CPU Accessibility: ...
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Register 58 TIMR2 Timer Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 59 TIMR3 Timer Register 3 CPU Accessibility: ...
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SRC Clock Source (valid in clock mode 5 only) This bit selects the clock source of the internal timer: SRC = ’0’ SRC = ’1’ TMD Timer Mode This bit must be set to ’1’ if HDLC Automode operation is ...
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TVALUE Timer Expiration Value (23:0) This bit field determines the timer expiration period ’t’: (’CP’ is the clock period, depending on bit ’SRC’.) Data Sheet Register Description (TIMR3 × t TVALUE 5-181 PEB 20525 ...
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Register 60 XAD1 Transmit Address 1 Register CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 61 XAD2 Transmit Address 2 Register ...
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XAD1 and XAD2 bit fields are valid in HDLC modes with automatic address field handling only (Automode, Address Mode 1, Address Mode 2). They can be programmed with one individual address byte which is inserted automatically into the address field ...
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Register 62 RAL1 Receive Address 1 Low Register CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 63 RAH1 Receive Address 1 ...
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Register 64 RAL2 Receive Address 2 Low Register CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 65 RAH2 Receive Address 2 ...
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In operating modes that provide address recognition, the high/low byte of the received address is compared with the individually programmable values in register RAH2/ RAL2/RAH1/RAL1. This addresses can be masked on a per bit basis by setting the corresponding bits ...
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Register 66 AMRAL1 Mask Receive Address 1 Low Register CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 67 AMRAH1 Mask Receive ...
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Register 68 AMRAL2 Mask Receive Address 2 Low Register CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 69 AMRAH2 Mask Receive ...
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AMRAH2 Receive Mask Address 2 Byte High AMRAL2 Receive Mask Address 2 Byte Low AMRAH1 Receive Mask Address 1 Byte High AMRAL1 Receive Mask Address 1 Byte Low Setting a bit in this registers to ’1’ masks the corresponding bit ...
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Register 70 RLCRL Receive Length Check Register (Low Byte) CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 Register 71 RLCRH Receive Length ...
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RCE Receive Length Check Enable This bit is valid in HDLC mode only and enables/disables the receive length check function: RCE = ’0’ RCE = ’1’ RL(10:0) Receive Length Check Limit This bit-field defines the receive length check limit (32..65536 ...
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Register 72 ISR0 Interrupt Status Register 0 CPU Accessibility: read only Reset Value Channel A Offset Address typical usage: updated by SEROCCO-H read and evaluated by CPU Bit 7 6 RDO RFO Register 73 ISR1 Interrupt ...
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Register 74 ISR2 Interrupt Status Register 2 CPU Accessibility: read only Reset Value Channel A Offset Address typical usage: updated by SEROCCO-H read and evaluated by CPU Bit Data Sheet Channel B ...
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RDO Receive Data Overflow Interrupt This bit is set to ’1’, if receive data of the current frame got lost because of a SCC receive FIFO full condition. However the rest of the frame is received and discarded as long ...
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RME Receive Message End Interrupt This bit set to ’1’ indicates that the reception of one message is completed, i.e. either – one message which fits into RFIFO not exceeding the receive FIFO threshold, or – the last part of ...
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XMR Transmit Message Repeat This bit is set to ’1’, if transmission of the last frame has to be repeated (by software), because • the SCC has received a negative acknowledge to an I-frame (in HDLC Automode operation); • a ...
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XDU Transmit Data Underrun Interrupt This bit is set to ’1’, if the current frame was terminated by the SCC with an abort sequence, because neither a ’frame end’ indication was detected in the FIFO (to complete the current frame) ...
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Register 75 IMR0 Interrupt Mask Register 0 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit 7 6 RDO RFO Register 76 IMR1 Interrupt Mask ...
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Register 77 IMR2 Interrupt Mask Register 2 CPU Accessibility: read/write Reset Value Channel A Offset Address typical usage: written by CPU; read and evaluated by SEROCCO-H Bit Data Sheet Channel B A6 ...
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Interrupt Mask Bits Each SCC interrupt event can generate an interrupt signal indication via pin INT/INT. Each bit position of registers corresponding interrupt event in the interrupt status registers ISR0..ISR2. Masked interrupt events never generate an interrupt indication via ...