PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 200

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Data Sheet
(IM)
Interrupt Mask Bits
Each SCC interrupt event can generate an interrupt signal indication via
pin INT/INT. Each bit position of registers
corresponding interrupt event in the interrupt status registers
ISR0..ISR2. Masked interrupt events never generate an interrupt
indication via pin INT/INT.
bit = ’0’
bit = ’1’
Moreover, masked interrupt events are:
• not displayed in the interrupt status registers
• displayed in interrupt status registers
Note: After RESET, all interrupt events are masked. Undefined bits must
For detailed interrupt event description refer to the corresponding bit
position in registers ISR0..ISR2.
register
CCR0L
not be cleared to ’0’.
is programmed to ’1’.
CCR0L
The corresponding interrupt event is NOT masked and will
generate an interrupt indication via pin INT/INT.
The corresponding interrupt event is masked and will
NEITHER generate an interrupt vector NOR an interrupt
indication via pin INT/INT.
is programmed to ’0’.
5-200
ISR0..ISR2
IMR0..IMR2
Register Description (IMR2)
ISR0..ISR2
if bit ’VIS’ in register
is a mask for the
PEB 20525
PEF 20525
if bit ’VIS’ in
2000-09-14