PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 85

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

the auto-mode, all others in the non auto-mode. HDLC frames with address fields that
do not match any of the address combinations, are ignored by the SCC.
In the case of a 1-byte address, only
According to the X.25 LAPB protocol, the value in
COMMAND and the value in
The address bytes can be masked to allow selective broadcast frame recognition. For
further information see
4.1.0.2
Characteristics: address recognition, arbitrary window size.
All frames with valid addresses (address recognition identical to auto-mode) are
forwarded directly to the RFIFO.
The HDLC control field, I-field data and an additional status byte are temporarily stored
in the SCC receive FIFO.
In address mode 2, all frames with a valid address are treated similarly.
The address bytes can be masked to allow selective broadcast frame recognition.
4.1.0.3
Characteristics: address recognition high byte.
Only the high byte of a 2-byte address field will be compared. The address byte is
compared with the fixed value FE
individually programmable values
address byte will be stored in the SCC receive FIFO.
The address bytes can be masked to allow selective broadcast frame recognition.
4.1.0.4
Characteristics: no address recognition
No address recognition is performed and each complete frame will be stored in the SCC
receive FIFO.
4.1.1
The following figures give an overview about the management of the received frames in
the different HDLC operating modes. The graphics show the actual HDLC frame and
how SEROCCO-H interprets the incoming octets. Below that it is shown which octets are
stored in the RFIFO and will thus be transferred into memory.
Data Sheet
Address Mode 2
Address Mode 1
Address Mode 0
HDLC Receive Data Processing
“Receive Address Handling” on Page
RAL2
RAH1
as RESPONSE.
RAL1
H
or FC
and RAH2. The whole frame excluding the first
and
85
H
RAL2
(group address) as well as with two
will be used as comparison values.
Detailed Protocol Description
RAL1
will be interpreted as
88.
PEB 20525
PEF 20525
2000-09-14