PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 48

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

The internal structure of each SCC channel consists of a transmit protocol machine
clocked with the transmit frequency f
receive frequency f
The clocks f
clock inputs e.g. f
The features of the different clock modes are summarized in
Table 8
Clock
Mode
CCR0L:
CM(2..0)
0a
0b
1
2a
2b
3a
3b
4
5a
5b
6a
6b
7a
7b
Note: If one of the clock modes 0b, 6 or 7 is selected, the internal oscillator (OSC) should
The first two columns of
and bit ’SSEL’ in register CCR0L.
For example, clock mode 6b is choosen by writing a ’6’ to register CCR0L.CM(2:0) and
by setting bit CCR0L.SSEL equal to ’1’. The following 4 columns (grouped as ’Clock
Sources’) specify the source of the internal clocks. Columns REC and TRM correspond
to the domain clock frequencies f
The columns grouped as ’Control Sources’ cover additional clock mode dependent
control signals like strobe signals (clock mode 1), clock gating signals (clock mode 4) or
Data Sheet
Configuration
Channel
be enabled by clearing bit GMODE:OSCPD. This allows connection of an external
crystal to pins XTAL1-XTAL2. The output signal of the OSC can be used for one
serial channel, or for both serial channels (independent baud rate generators and
DPLLs). Moreover, XTAL1 alone can be used as input for an externally generated
clock.
CCR0L:
SSEL
0
1
X
0
1
0
1
X
0
1
0
1
0
1
TRM
Clock Modes of the SCCs
to
BRG
–
OSC
–
RxCLK
RxCLK
RxCLK
RxCLK
–
–
–
OSC
OSC
OSC
OSC
and f
TRM
REC
and TxCLK input pin.
REC
.
to
DPLL
–
–
–
BRG
BRG
BRG
–
–
–
–
BRG
BRG
BRG
–
Table 8
Clock Sources
are internal clocks only and need not be identical to external
to
REC
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
list all possible clock modes configured via bit field ’CM’
REC
TRM
and f
to
TRM
TxCLK
BRG
RxCLK
TxCLK
BRG/16
DPLL
BRG
TxCLK
RxCLK
TxCLK
TxCLK
BRG/16
DPLL
BRG
and a receive protocol machine clocked with the
TRM
48
CD
CD
CD
–
CD
CD
CD
CD
–
–
–
CD
CD
CD
CD
.
R- Strobe
–
–
CD
–
–
–
–
RCG
(TSAR/
PCMRX)
(TSAR/
PCMRX)
–
–
–
–
Control Sources
Table
X- Strobe
–
–
TxCLK
–
–
–
–
TCG
(TSAX/
PCMTX)
(TSAX/
PCMTX)
–
–
–
–
Functional Overview
8.
Frame-
Sync
Tx
–
–
–
–
–
–
–
–
FSC
OST
–
–
–
–
–
–
–
–
–
–
–
–
FSC
OSR
–
–
–
–
PEB 20525
PEF 20525
Rx
2000-09-14
Output
via
TxCLK
(if CCR0L:
TOE = ‘1’)
–
BRG
–
–
BRG/16
DPLL
BRG
-
TS-Control
–
–
BRG/16
DPLL
BRG