PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 35

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PEF 20525 F V1.3

Manufacturer Part Number
PEF 20525 F V1.3
Description
IC CTRL PPP/HDLC SERIAL TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20525 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20525FV1.3X
PEF20525FV13XP
SP000007592
Table 3
Pin No.
P-
LFBGA-
80-2
F3
F2
Data Sheet
P-TQFP-
100-3
17
13
Serial Port Pins
Symbol In (I)
TxCLK
A
RxCLK
A
Out (O)
I/O
I
Function
Transmit Clock Channel A
The function of this pin depends on the selected
clock mode and the value of bit ’TOE’
register, refer to
SCCs" on Page
If programmed as Input (CCR0L.TOE=’0’),
either
– the transmit clock for the channel (clock
– a transmit strobe signal for the channel (clock
can be provided to this pin.
If programmed as Output (CCR0L.TOE=’1’),
this pin supplies either
– the transmit clock from the baud rate generator
– the transmit clock from the DPLL circuit (clock
– an active-low control signal marking the
Receive Clock Channel A
The function of this pin depends on the selected
clock mode (refer to
the SCCs" on Page
A signal provided on pin RxCLKA may supply
– the receive clock (clock mode 0, 4, 5b), or
– the receive and transmit clock (clock mode 1,
– the clock input for the baud rate generator
mode 0a, 2a, 4, 5b, 6a), or
mode 1)
(clock mode 0b, 2b, 3b, 6b, 7b), or
mode 3a, 7a), or
programmed transmit time-slot in clock mode
5a.
5a), or
(clock mode 2, 3).
35
Table 8 "Clock Modes of the
48).
Table 8 "Clock Modes of
48).
Pin Descriptions
PEB 20525
PEF 20525
(CCR0L
2000-09-14

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