PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 83

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

4
The following
desired protocol mode is selected via bit fields in the channel configuration registers
CCR2L
Table 12
1)
All modes are discussed in details in this chapter.
4.1
The HDLC controller of each serial channel (SCC) can be programmed to operate in
various modes, which are different in the treatment of the HDLC frame in receive
direction. Thus, the receive data flow and the address recognition features can be
performed in a very flexible way satisfying almost any application specific requirements.
There are 4 different HDLC operating modes which can be selected via register bits
CCR2L:MDS[1:0] and CCR2L:ADM.
The following table provides an overview of the different address comparison
mechanisms in HDLC operating modes:
Data Sheet
Protocol Mode
HDLC Automode
(LAP D / LAP B / SDLC-NRM)
HDLC Address Mode 2
HDLC Address Mode 1
HDLC Address Mode 0
Signaling System #7 (SS7) Operation
Bit Synchronous PPP Mode
Octet Synchronous PPP Mode
Extended Transparent Mode
Extended transparent mode is a fully bit-transparent transmission/reception mode.
and CCR3L.
Detailed Protocol Description
HDLC/SDLC Protocol Modes
Table 12
Protocol Mode Overview
provides an overview of all supported protocol modes and . The
1)
16 bit
8 bit
16 bit
8 bit
83
Register
MDS
’00’
’00’
’01’
’01’
’10’
’10’
’10’
’10’
’11’
CCR2L
Detailed Protocol Description
ADM
’1’
’0’
’1’
’0’
’1’
’0’
’0’
’0’
’1’
- Bit Field:
’00’
’00’
’11’
’01’
’00’
PPPM
PEB 20525
PEF 20525
2000-09-14
CCR3L
ESS7
’0’
’1’
’0’
’0’