PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 204
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PEF 20525 F V1.3
Manufacturer Part Number
PEF 20525 F V1.3
Description
IC CTRL PPP/HDLC SERIAL TQFP-100
Manufacturer
Infineon Technologies
Datasheet
1.PEB_20525_F_V1.3.pdf
(252 pages)
Specifications of PEF 20525 F V1.3
Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20525FV1.3X
PEF20525FV13XP
SP000007592
PEF20525FV13XP
SP000007592
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Data Sheet
C/R
LA
Command/Response
Significant only if 2-byte address mode has been selected.
Value of the C/R bit (bit 1 of high address byte) in the received frame.
The interpretation depends on the setting of the ’CRI’ bit in the
register (See “RAH1” on page 184.).
Low Byte Address Compare
Significant in automode and address mode 2 only.
The low byte address of a 2-byte address field, or the single address byte
of a 1-byte address field is compared with two addresses (RAL1, RAL2).
LA=’0’
LA=’1’
According to the X.25 LAPB protocol,
of a COMMAND frame and
RESPONSE frame.
RAL2
RAL1
has been recognized.
has been recognized.
5-204
RAL2
is interpreted as the address of a
RAL1
Register Description (RSTA)
is interpreted as the address
PEB 20525
PEF 20525
2000-09-14
RAH1
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