PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 135

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Data Sheet
Register 19
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 20
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
The command register contains self-clearing command bits. The command bits read a
’1’ until the corresponding command is executed completely.
For a write access to the register, the new value gets OR’ed with the current register
contents.
The ’CEC’ bit in register
Bit
Bit
RMC
STI
7
7
Timer
CMDRL
Command Register (Low Byte)
TRES
CMDRH
Command Register (High Byte)
RNR
6
6
read/write
00
Channel A
14
written by CPU, evaluated by SEROCCO-H
read/write
00
Channel A
15
written by CPU, evaluated by SEROCCO-H
H
H
H
H
STARL/STARH
XIF
5
5
0
Channel B
64
Channel B
65
Receiver Commands
H
H
XRES
is the OR-function over all command bits.
5-135
4
4
0
Transmitter Commands
RSUC
XF
3
3
Register Description (CMDRL)
XME
2
2
0
XREP
1
1
0
PEB 20525
PEF 20525
2000-09-14
RRES
0
0
0