PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 42

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PEF 20525 F V1.3

Manufacturer Part Number
PEF 20525 F V1.3
Description
IC CTRL PPP/HDLC SERIAL TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20525 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20525FV1.3X
PEF20525FV13XP
SP000007592
3
The functional blocks of SEROCCO-H can be divided into two major domains:
– the microprocessor interface of SEROCCO-H provides access to on-chip registers
– the Serial Communication Controller (SCC) is capable of processing bit-synchronous
Data exchange between the serial communication controller and the microprocessor
interface is performed using FIFOs, decoupling these two domains.
3.1
Figure 9
Data Sheet
and to the "user" portion of the receive and transmit FIFOs (RFIFO/XFIFO). Optionally
these FIFOs can be accessed by an external 4-channel DMA controller.
(HDLC/SDLC/bitsync PPP) and octet-synchronous (octet-sync PPP) as well as fully
transparent data traffic.
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6
Functional Overview
Block Diagram
External DMA
Block Diagram
Interface
Transmit FIFO
Transmit FIFO
Receive FIFO
Receive FIFO
(32 Byte)
(32 Byte)
(32 Byte)
(32 Byte)
JTAG Test
Interface
5
Serial Channel A
Serial Channel B
Transmit FIFO
Receive FIFO
(32 Byte)
(32 Byte)
42
LAP Control
Transmit
Machine
Machine
Protocol
Receive
Protocol
TSA
Functional Overview
Decoder/
Collision
Detection
DPLL
Clock
Control
Oscillator
BRG
PEB 20525
PEF 20525
2000-09-14
7
7

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