PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 201

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Data Sheet
Register 78
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
The Receive Status Byte ’RSTA’ contains comprehensive status information about the
last received frame (HDLC/PPP).
The SCC attaches this status byte to the receive data and thus it should be read from
the RFIFO.
In HDLC/PPP modes the RSTA value can optionally be read from this register address.
In extended transparent mode this status field does not apply.
Bit
VFR
7
RSTA
Receive Status Byte
RDO
6
written by SEROCCO-H to RFIFO;
read only
00
Channel A
58
read from RFIFO and evaluated by CPU
H
H
CRCOK
5
Channel B
A8
Receive Status Byte
H
RAB
5-201
4
3
HA(1:0)/
SU(1:0)
Register Description (RSTA)
2
C/R
1
PEB 20525
PEF 20525
2000-09-14
LA
0