PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 49

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

PEB 20525
PEF 20525
Functional Overview
synchronization signals (clock mode 5). The last column describes the function of signal
TxCLK which in some clock modes can be enabled as output signal monitoring the
effective transmit clock or providing a time slot control signal (clock mode 5).
The following is an example of how to read
Table
8:
For clock mode 6b (row ’6b’) the TRM clock (column ’TRM’) is supplied by the baudrate
generator (BRG) output divided by 16 (source BRG/16). The BRG (column ’BRG’) is
derived from the internal oscillator which is supplied by pin XTAL1 and XTAL2.
The REC clock (column ’REC’) is supplied by the internal DPLL which itself is supplied
by the baud rate generator (column ’DPLL’) again.
Note: The REC clock is DPLL clock divided by 16.
If enabled by bit ’TOE’ in register
CCR0L
the resulting transmit clock can be monitored
via pin TxCLK (last column, row ’6b’).
Data Sheet
49
2000-09-14