PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 111

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PEF 20525 F V1.3

Manufacturer Part Number
PEF 20525 F V1.3
Description
IC CTRL PPP/HDLC SERIAL TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20525 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20525FV1.3X
PEF20525FV13XP
SP000007592
5.2
5.2.1
Each register description is organized in three parts:
• a head with general information about reset value, access type (read/write), offset
• a table containing the bit information (name of bit positions);
• a section containing the detailed description of each bit.
Register 1
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Data Sheet
SWR
Bit
address and usual handling;
7
0
Detailed Register Description
Global Registers
Software Reset Command
Self clearing command bit:
bit=’0’
bit=’1’
Global Command Register
GCMDR
6
0
read/write
00
00
written by CPU,
evaluated by SEROCCO-H
H
H
No software reset command is issued.
Causes SEROCCO-H to perform a complete reset
identical to hardware reset.
5
0
Global Command Bits
4
0
111
3
0
2
0
Register Description
1
0
PEB 20525
PEF 20525
2000-09-14
SWR
0

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