PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 75

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

– Manchester (also known as Bi-Phase)
The desired line coding scheme can be selected via bit field ’SC(2:0)’ in register CCR0H.
3.2.13.1 NRZ and NRZI Encoding
NRZ: The signal level corresponds to the value of the data bit. By programming bit ’DIV’
(CCR1L
NRZI: A logical ‘0’ is indicated by a transition and a logical ‘1’ by no transition at the
beginning of the bit cell.
Figure 33
3.2.13.2 FM0 and FM1 Encoding
FM0: An edge occurs at the beginning of every bit cell. A logical ‘0’ has an additional
edge in the center of the bit cell, whereas a logical ‘1’ has none. The transmit clock
precedes the receive clock by 90 ° .
FM1: An edge occurs at the beginning of every bit cell. A logical ‘1’ has an additional
edge in the center of the bit cell, a logical ‘0’ has none. The transmit clock precedes the
receive clock by 90 ° .
Data Sheet
Receive Clock
Transmit
NRZ
NRZI
register), the SCC may invert the transmission and reception of data.
/
NRZ and NRZI Data Encoding
0
1
1
75
0
0
1
Functional Overview
0
PEB 20525
PEF 20525
ITD05313
2000-09-14