PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 32

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Table 1
Pin No.
P-
LFBGA-
80-2
H9
H2
Data Sheet
P-TQFP-
100-3
54
19
Microprocessor Bus Interface
Symbol In (I)
READY
DTACK
RESET I
Out (O)
O
O
Function
Ready (Intel bus mode)
Data Transfer Acknowledge (Motorola mode)
During a slave access (register read/write) this
signal (output) indicates, that the SEROCCO-H is
ready for data transfer. The signal remains active
until the data strobe (DS in Motorola bus mode,
RD/WR in Intel bus mode) and/or the chip select
(CS) go inactive.
This line is tri-state when unused.
A pull-up resistor to V
function is not used.
Reset
With this active low signal the on-chip registers
and state machines are forced to reset state.
During Reset all pins are in a high impedance
state.
32
DD3
is recommended if this
Pin Descriptions
PEB 20525
PEF 20525
2000-09-14