PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 33

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Table 2
Pin No.
P-
LFBGA-
80-2
A9
A8
B7
Data Sheet
P-TQFP-
100-3
84
86
85
External DMA Interface
Symbol In (I)
DRTA
DRRA
DACKA I
Out (O)
O
O
Function
DMA Request Transmitter Channel A
The transmitter on a this channel requests a DMA
transfer by activating the DRTA line. The request
remains active as long as the Transmit FIFO
requires data transfers. The amount of data bytes
to be transferred from the system memory to the
serial channel (= Byte Count) must be written first
to the XBCL,
data (n x 32 bytes + rest ; n=0,1,…) are
transferred till the Byte Count is reached. DRTA is
deactivated with the beginning of the last write
cycle.
DMA Request Receiver Channel A
The receiver on this serial channel requests a
DMA transfer by activating the DRRA line. The
request remains active as long as the Receive
FIFO requires data transfers, thus always blocks
of data are transferred. DRRA is deactivated
immediately following the falling edge of the last
read cycle.
DMA Acknowledge Channel A
A low signal on this pin informs the SEROCCO-H
that the requested DMA cycle controlled via
DRTA or DRRA of this channel is in progress, i.e.
the DMA controller has achieved bus mastership
from the CPU and will start data transfer cycles
(either write or read). In conjunction with a read or
write operation this input serves as Access
Enable (similar to CS) to the respective FIFOs. If
DACKA is active, the input to pins A(7:0) and CS
is ignored and the FIFOs are implicitly selected.
If not used, a pull-up resistor to V
this pin.
33
XBCH
registers. Always blocks of
Pin Descriptions
DD
is required for
PEB 20525
PEF 20525
2000-09-14