PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 58

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Note: If time-slot 0 is to be selected, the DELAY has to be as long as the PCM frame
Note: In extended transparent mode the width xCC of the selected time-slot has to be
Data Sheet
itself to achieve synchronization (at least for the 2nd and subsequent PCM
frames): DELAY = PCM frame length = 1 + xTSN*8 + xCS. xTSN and xCS have
to be set appropriately.
Example: Time-slot 0 in E1 (2.048 Mbit/s) system has to be selected.
PCM frame length is 256 clocks. 256 = 1+ xTSN*8 + xCS. => xTSN = 31, xCS = 7.
n ´ 8 bit because of character synchronization (byte alignment). In all other modes
the width can be used to define windows down to a minimum length of one bit.
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Functional Overview
PEB 20525
PEF 20525
2000-09-14