PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 218

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

1) A receive threshold of 32 bytes is the default for HDLC/PPP mode. It can be programmed with bit field
2) The number of bytes stored in RFIFO can be determined by evaluating the lower bits in register (depending
Figure 54
Data Sheet
RFTH(1:0) in register .
on the selected receive threshold RFTH(1:0)).
Interrupt Driven Data Reception (Flow Diagram)
bytes from RFIFO
Interrupt
'RPF'
Read
[32]
1)
Activate Receiver
(CMDRH.RRES)
Release RFIFO
(CMDRH.RMC)
Reset Receiver
(CCR3L.RAC)
INTERRUPT
WAIT FOR
START
218
bytes from RFIFO
(Rc Byte Count)
Read registers
RBCL, RBCH
[RBCL % 32]
'RME'/'TCD'
Interrupt
Read
1), 2)
Action taken
by CPU
Interrupt
indication to CPU
Programming
PEB 20525
PEF 20525
2000-09-14