PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 113

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Data Sheet
OSCPD
DSHP
GIM
Oscillator Power Down
Setting this bit to ’0’ enables the internal oscillator. For power saving
purposes (escpecially if clock modes are used which do not need the
internal oscillator) this bit may remain set to ’1’.
OSCPD=’0’
OSCPD=’1’
Note: After reset this bit is set to ’1’, i.e. the oscillator is in power down
Disable Shaper
This bit has to be set to ’0’ if the shaping function in the oscillator unit is
desired. The shaper amplifies the oscillator signal and improves the
slope of the clock edges.
DSHP=’0’
DSHP=’1’
Note: After reset this bit is set to ’1’, i.e. the shaper is disabled!
Global Interrupt Mask
This bits disables all interrupt indications via pin INT/INT. Internal
operation (interrupt generation, interrupt status register update,...) is not
affected.
If set, pin INT/INT immediately changes or remains in inactive state.
GIM=’0’
GIM=’1’
Note: After reset this bit is set to ’1’, i.e. all interrupts are disabled!
mode!
The internal oscillator is active.
The internal oscillator is in power down mode.
Shaper is enabled. Recommended setting if a crystal is
connected to pins XTAL1/XTAL2.
Shaper is disabled (bypassed). Recommended setting if
- a TTL level clock signal is supplied to pin XTAL1
- the oscillator unit is unused
Global interrupt mask is cleared. Pin INT/INT is controlled
by the internal interrupt control logic and activated as long
as at least one unmasked interrupt indication is pending
(not yet confirmed by read access to corresponding
interrupt status register).
Global interrupt mask is set. Pin INT/INT remains inactive.
5-113
Register Description (GMODE)
PEB 20525
PEF 20525
2000-09-14