PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 189

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PEF 20525 F V1.3

Manufacturer Part Number
PEF 20525 F V1.3
Description
IC CTRL PPP/HDLC SERIAL TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20525 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20525FV1.3X
PEF20525FV13XP
SP000007592
Data Sheet
AMRAH2
AMRAL2
AMRAH1
AMRAL1
Receive Mask Address 2 Byte High
Receive Mask Address 2 Byte Low
Receive Mask Address 1 Byte High
Receive Mask Address 1 Byte Low
Setting a bit in this registers to ’1’ masks the corresponding bit in
registers RAH2/RAL2/RAH1/RAL1. A masked bit position always
matches when comparing the received frame address with registers
RAH2/RAL2/RAH1/RAL1, allowing extended broadcast mechanism.
bit = ’0’
bit = ’1’
The dedicated bit position is NOT masked. This bit
position in the received address must match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1
The dedicated bit position is masked. This bit position in
the received address NEED NOT match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1
to accept the frame.
to accept the frame.
5-189
Register Description (AMRAH2)
PEB 20525
PEF 20525
2000-09-14

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