PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 217

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

6.2.2
Also 2 ´
direction.
There are different interrupt indications concerned with the reception of data:
•
•
In addition to the message end (’RME’) interrupt the following information about the
received packet is stored by SEROCCO-H in special registers and/or RFIFO:
Table 16
Status Information
Length of received message
CRC result (good/bad)
Valid frame (yes/no)
ABORT sequence recognized (yes/no)
Data overflow (yes/no)
Results from address comparison
(with automatic address handling)
Type of frame (COMMAND/RESPONSE)
(with automatic address handling)
Type of Signaling Unit
(in SS7 mode)
Note: After the received data has been read from the RFIFO, this must be explicitly
The data reception sequence, from the CPU’s point of view, is outlined in
Data Sheet
’
with the receive FIFO threshold in register CCR3H, bit field ’RFTH(1..0)’; default is 32
bytes) can be read from RFIFO and the received message is not yet complete.
’
is completed, i.e. either
- one message which fits into RFIFO not exceeding the receive FIFO threshold, or
- the last part of a message, all in all exceeding the receive FIFO threshold
is stored in the RFIFO.
RPF’ (Receive Pool Full) interrupt, indicating that a specified number of bytes (limited
RME’ (Receive Message End) interrupt, indicating that the reception of one message
acknowledged by the CPU issuing an ’RMC’ (Receive Message Complete)
command. The CPU has to handle the ’RPF’ interrupt before the complete 2 x 32-
byte FIFO is filled up with receive data which would cause a “Receive Data
Overflow” condition.

32 byte FIFO buffers (receive pools) are provided for each channel in receive
Data Reception (Interrupt Driven)
Status Information after RME interupt
217
Location
registers RBCH,
RSTA
RSTA
RSTA
RSTA
RSTA
RSTA
RSTA
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
register (or last byte of received data)
RBCL
Programming
Figure
PEB 20525
PEF 20525
2000-09-14
54.