PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 67

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

3.2.3.9
This clock mode is identical to clock mode 3a/3b except that the clock source of the BRG
is supplied at pin XTAL1.
The BRG is driven by the internal oscillator. Depending on the value of bit ’SSEL’ in
register
the resulting DPLL output frequency (clock mode 7a) or delivers directly the receive and
transmit clock (clock mode 7b). In clock mode 7a the DPLL output clocks receive and
transmit data.
Figure 28
Data Sheet
CCR0L
Clock Mode 7 (7a/7b)
Clock Mode 7a/7b Configuration
clock mode 7a
clock mode 7b
the BRG delivers either a reference clock for the DPLL which is 16 times
or
or
DPLL
OSC
BRG
OSC
BRG
Ctrl.
Ctrl.
Ctrl.
Ctrl.
67
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
(tx clock monitor output)
(tx clock monitor output)
V
V
SS
SS
Functional Overview
PEB 20525
PEF 20525
2000-09-14