PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 195

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Data Sheet
RME
RFS
FLEX
TIN
CSC
Receive Message End Interrupt
This bit set to ’1’ indicates that the reception of one message is
completed, i.e. either
– one message which fits into RFIFO not exceeding the receive FIFO
– the last part of a message, all in all exceeding the receive FIFO
is stored in the RFIFO.
The complete message length can be determined by reading the RBCL/
RBCH
4, 2 or 1 least significant bits of register RBCL, depending on the
selected RFIFO threshold (bit field ’RFTH(1:0)’ in register CCR3H).
Additional frame status information is available in the
in the RFIFO as the last byte of each frame.
Note: After the RFIFO contents have been read, an CMDRH:RMC
Receive Frame Start Interrupt
This bit is set to ’1’, if the beginning of a valid frame is detected by the
receiver. A valid frame start is detected either if a valid address field is
recognized (in all operating modes with address recognition) or if a start
flag is recognized (in all operating modes with no address recognition).
Frame Length Exceeded Interrupt
This bit is set to ’1’, if the frame length check feature is enabled and the
current received frame is aborted because the programmed frame length
limit was exceeded (refer to registers
description).
Timer Interrupt
This bit is set to ’1’, if the internal timer was activated and has expired
(refer also to description of timer registers TIMR0..TIMR3).
CTS Status Change
This bit is set to ’1’, if a transition occurs on signal CTS. The current state
of signal CTS is monitored by status bit ’CTS’ in status register STARL.
Note: A transmit clock must be provided to detect a transition of CTS.
threshold, or
threshold
command must be issued to free the RFIFO for new receive data.
registers. The number of bytes stored in RFIFO is given by the 5,
5-195
RLCRL/RLCRH
Register Description (ISR2)
RSTA
PEB 20525
byte, stored
PEF 20525
for detailed
2000-09-14