PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 238

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PEF 20525 F V1.3

Manufacturer Part Number
PEF 20525 F V1.3
Description
IC CTRL PPP/HDLC SERIAL TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20525 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Bit Processor Functions, Serial Communication Controllers (SCCs)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20525FV1.3X
PEF20525FV13XP
SP000007592
7.7.2.2
Figure 72
Table 25
No. Parameter
90
91
92
Data Sheet
Receive
data rates
(1) Whichever supplies the receive clock depending on the selected clock mode:
(2) NRZ, NRZI and Manchester data encoding
(3) FM0 and FM1 data encoding
(4) If Carrier Detect auto start feature enabled (not for clock modes 1, 4 and 5)
Receive Clock
externally clocked via RxCLK or XTAL1 or
internally clocked via DPLL or BRG.
(No edge relation can be measured if the internal receive clock is derived from the external clock
source by division stages (BRG) or DPLL)
Clock
period
RxD to RxCLK setup time
RxD to RxCLK hold time
(Note 1)
(Note 2)
(Note 3)
(Note 4)
Receive Cycle Timing
RxD
RxD
Receive Cycle Timing
Receive Cycle Timing
CD
externally clocked
(HDLC)
internally clocked
(DPLL modes)
internally clocked
(non DPLL modes)
externally clocked
internally clocked
(DPLL modes)
internally clocked
(non DPLL modes)
91
93
92
238
91
91
90
94
92
92
min.
0
0
0
80
480
80
5
5
Electrical Characteristics
Limit Values
max.
12.5
2
12.5
¥
¥
¥
PEB 20525
PEF 20525
2000-09-14
Unit
Mbit/s
Mbit/s
Mbit/s
ns
ns
ns
ns
ns

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