PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 84

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

Table 13
Mode
4.1.0.1
Characteristics: Window size 1, random message length, address recognition.
The SCC processes autonomously all numbered frames (S-, I-frames) of an HDLC
protocol. The HDLC control field, I-field data of the frames and an additional status byte
are temporarily stored in the SCC receive FIFO.
Depending on the selected address mode, the SCC can perform a 2-byte or 1-byte
address recognition.
If a 2-byte address field is selected, the high address byte is compared with the fixed
value FE
in
byte address will be interpreted as COMMAND/RESPONSE bit (C/R), depending on the
setting of the CRI bit in RAH1, and will be excluded from the address comparison.
Similarly, two comparison values can be programmed in special registers (RAL1, RAL2)
for the low address byte. A valid address will be recognized in case the high and low byte
of the address field correspond to one of the compare values. Thus, the SCC can be
called (addressed) with 6 different address combinations, however, only the logical
connection identified through the address combination
Data Sheet
Address
Address
Address
Mode 2
Mode 1
Mode 0
RAH1
Mode
Auto
-
H
and
or FC
Automode
Address
Field
16 bit
8 bit
8 bit
None
RAH2
Address Comparison Overview
H
(group address) as well as with two individually programmable values
registers. According to the ISDN LAPD protocol, bit 1 of the high
FE
FE
FE
H
H
H
High Address Byte
/ FC
/ FC
/ FC
don’t care
H
H
H
Recognized Address Bytes for a Match:
(1111 11 C/R 0
(1111 11 C/R 0
(1111 11 C/R 0
RAH1
RAH1
RAH2
RAH2
RAH1
RAH2
RAL1
RAL2
84
2
2
2
)
)
)
RAH1/RAL1
and
and
and
and
and
and
Detailed Protocol Description
Low Address Byte
will be processed in
don’t care
don’t care
don’t care
don’t care
don’t care
don’t care
RAL1
RAL2
RAL1
RAL2
RAL1
RAL2
PEB 20525
PEF 20525
2000-09-14