PEF 20525 F V1.3 Infineon Technologies, PEF 20525 F V1.3 Datasheet - Page 56

• Manufacturer Part Number: PEF 20525 F V1.3
• Description: IC CTRL PPP/HDLC SERIAL TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20525 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Bit Processor Functions, Serial Communication Controllers (SCCs)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20525FV1.3X; PEF20525FV13XP; SP000007592

3.2.3.6
This operation mode has been designed for application in time-slot oriented PCM
systems.
Note: For correct operation NRZ data coding/encoding should be used.
The receive and transmit clock are common for each channel and must be supplied
externally via pin RxCLK. The SCC receives and transmits only during fixed time-slots.
Either one time-slot
– of programmable width (1 … 512 bit, via TTSA and RTSA registers), and
– of programmable location with respect to the frame synchronization signal (via pin
or up to 32 time-slots
– of constant width (8 bits), and
– of programmable location with respect to the frame synchronization signal (via pin
can be selected.
The time-slot locations can be programmed independently for receive and transmit
direction via TTSA/RTSA and PCMTX/PCMRX registers.
Depending on the value programmed via those registers, the receive/transmit time-slot
starts with a delay of 1 (minimum delay) up to 1024 clock periods following the frame
synchronization signal.
Figure 20
Figure 21
If bit ’TOE’ in register
an output status signal via pin TxCLK, which is driven to ‘low’ during the active transmit
window.
Bit ’TSCM’ in register
continuously running even if no synchronization pulse is detected at FSC signal or
stopping at their maximum value.
In the continuous case the repetition rate of offset counter operation is 1024 transmit or
receive clocks respectively. An FSC pulse detected earlier resets the counters and starts
operation again.
In the non-continuous case the time slot assigner offset counter is stopped after the
counter reached its maximum value and is started again if an FSC pulse is detected.
Data Sheet
FSC)
FSC)
shows how to select one or more time-slots of 8-bit width.
shows how to select a time-slot of programmable width and location and
Clock Mode 5a (Time Slot Mode)
CCR0L
CCR1H
is set, the selected transmit time-slot(s) is(are) indicated at
determines whether the internal offset counters are
56
Functional Overview
PEB 20525
PEF 20525
2000-09-14